Commit Graph

183651 Commits

Author SHA1 Message Date
Marek Olšák
03bc6156a3 radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT
Fixes: 25a66477d0 - radeonsi/gfx11: register changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 7d3a414662)
2024-03-14 11:44:22 +00:00
Marek Olšák
d5b22fa737 radeonsi: disable binning correctly on gfx11.5
Fixes: b44a886b84 - amd/common: add registers for gfx11.5

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 20445f296b)
2024-03-14 11:44:21 +00:00
Marek Olšák
724b1c197d amd/registers: add correct gfx11.x enums for BINNING_MODE
Fixes: ced3fbbcf9 - amd/registers: add gfx11.json

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
(cherry picked from commit 62d360c287)
2024-03-14 11:44:21 +00:00
Mike Blumenkrantz
7f56248fa7 zink: destroy batch states after copy context
the copy context contains its own batch states, so these must
not be destroyed yet

Fixes: b06f6e00fb ("zink: fix heap-use-after-free on batch_state with sub-allocated pipe_resources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28118>
(cherry picked from commit 7fd12a446d)
2024-03-14 11:44:20 +00:00
Iván Briano
2eb71d157c compiler/types: fix serialization of cooperative matrix
Encoding of cmat_desc is overwriting the base_type with the type of the
elements of the matrix.

Fixes: 2d0f4f2c17 ("compiler/types: Add support for Cooperative Matrix types")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28086>
(cherry picked from commit e1b66f9707)
2024-03-14 11:44:18 +00:00
Samuel Pitoiset
9e5f6d42d1 ac/nir: fix exporting NGG streamout outputs with implicit PrimId from VS/TES
With RADV, when VS/TES and FS are compiled separately, the PrimitiveId
is exported unconditionally because it's not possible to know if the
FS reads it or not. This happens with fast-link GPL and shader object.

Though, the PrimitiveID should be ignored when it's implicitly exported
because otherwise the stream output LDS offset is incorrect.

This fixes a bunch of failures with transform feedback and Zink/RADV
when shader object is enabled on RDNA3.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27981>
(cherry picked from commit d12984edb8)
2024-03-14 11:41:35 +00:00
Eric Engestrom
5b8ee85c1a .pick_status.json: Update to 9b6d6c1d2d 2024-03-14 08:39:49 +00:00
Eric Engestrom
90dcd95c0e docs: add sha256sum for 24.0.3 2024-03-14 00:11:24 +00:00
Eric Engestrom
c4d371fa7e VERSION: bump for 24.0.3 2024-03-13 23:59:54 +00:00
Eric Engestrom
7c2243b1db docs: add release notes for 24.0.3 2024-03-13 23:59:34 +00:00
Juan A. Suarez Romero
991396e823 v3d: fix line coords with perspective projection
The algorithm used to rendering smooth lines worked under the assumption
that line coords were in the [0, 1] range. This was correct when using
an orthogonal projection, but not when using a perspective projection.

With a perspective projection (where the value for 1/Wc set in the VPM
is not 1.0), line coords values are also affected by this projection, so
the values are not in this range.

To deal with this, we normalize the line coords using the Wc value so
the range becomes [0, 1], and the smooth line rendering works as
expected.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10496
Fixes: ee4d51f8b2 ("v3d: Add a lowering pass for line smoothing")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28072>
(cherry picked from commit 69fbd5cb90)
2024-03-11 16:43:05 +00:00
Juan A. Suarez Romero
0aeacc0883 v3d: add load_fep_w_v3d intrinsic
This intrinsic helps to read the W coordinate stored in the QPU register
when initializing the input data for the fragment shaders.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28072>
(cherry picked from commit 62e1dff256)
2024-03-11 16:43:05 +00:00
Pierre-Eric Pelloux-Prayer
ce73c8f829 radeonsi: try to disable dcc if compute_blit is the only option
COMPUTE contexts have no blitter so there are no fallback to
si_can_use_compute_blit failing.

One solution would be to disable DCC globally when a COMPUTE context is
created but I'm not 100% sure it's a good idea.

Until then this commit can fix a number of cases and will also prevent
crashing if si_compute_blit fails.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10296
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27295>
(cherry picked from commit e4f7754977)
2024-03-11 15:48:36 +00:00
Faith Ekstrand
bcad1274bb nvk: Disable the Out Of Range Address exception
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27927>
(cherry picked from commit cc74a819e4)
2024-03-11 15:32:41 +00:00
Faith Ekstrand
8ee75c66d3 nvk: Always wait for the FALCON in set_priv_reg
The previous version had an optimization where, instead of actually
waiting on the FALCON to return, it would just do a bunch of nops in
some cases.  This seems broken at least on Turing+ and results in
registers not ending up with the right values.  It only really shows up
when you set two registers back-to-back in which case the second
SET_PRIV_REG may mess up the first.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27927>
(cherry picked from commit 0ed7bce8e5)
2024-03-11 15:32:41 +00:00
Faith Ekstrand
ed886a26c7 nvk: Document the register name for the helper load workaround
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27927>
(cherry picked from commit df90d80d9d)
2024-03-11 15:32:27 +00:00
Mike Blumenkrantz
b775fb81e9 driconf: add radv_zero_vram for Crystal Project (1637730)
fixes #10666

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28079>
(cherry picked from commit 9a57b1df53)
2024-03-11 14:54:12 +00:00
Samuel Pitoiset
e9551eaf33 util/u_debug: fix parsing of "all" again
The current implementation is incorrect if the string starts with "all"
like "RADV_DEBUG=allbos".

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10741
Fixes: 0c42c79edf ("utils/u_debug: Fix parse of "all,<something else>")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28051>
(cherry picked from commit 433a3c262a)
2024-03-11 14:52:19 +00:00
Christian Gmeiner
c46abe651b etnaviv: Fix how we determine the max supported number of varyings
The driver is written that we should support ETNA_NUM_VARYINGS and reporting
a bigger number will cause some troubles. I had a quick look at galcore's
hw database and there are entries that report a higher value.

So I think what we want is to the minimum value of what kernel driver reports
and what the gallium driver should be able to handle.

Fixes: 84816c22e4 ("etnaviv: ask kernel for max number of supported varyings")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27923>
(cherry picked from commit 93255abe30)
2024-03-11 14:52:18 +00:00
Eric Engestrom
c93608ecf9 .pick_status.json: Update to 9a57b1df53 2024-03-11 14:52:09 +00:00
Vasily Khoruzhick
00de0668b5 lima: update expected CI failures
Backport-to: 23.3
Backport-to: 24.0
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24855>
(cherry picked from commit 4762d03391)
2024-03-10 01:51:34 +00:00
Vasily Khoruzhick
d45476c079 lima: gpir: abort compilation if load_uniform instrinsic src isn't const
GP supports indirect indexing of uniforms, but it's never been
implemented in GPIR, so just abort compilation instead of crashing an
app with assertion failure.

Backport-to: 23.3
Backport-to: 24.0
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24855>
(cherry picked from commit feccf4121b)
2024-03-10 01:51:29 +00:00
Vasily Khoruzhick
c679b07111 lima: ppir: use dummy program if FS has empty body
As per spec, any colors, or color components, associated with a fragment
that are not written by the fragment shader are undefined.

So we might as well just write vec4(1.0) to output, since HW doesn't allow
us to have an empty FS.

Backport-to: 23.3
Backport-to: 24.0
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24855>
(cherry picked from commit 6998c48f77)
2024-03-10 01:51:24 +00:00
Vasily Khoruzhick
41b3728135 lima: ppir: always use vec4 for output register
gl_FragDepth is a float, but the hardware still uses a vec4 register,
.x component for depth and another component for stencil, so we have to
always allocate a vec4 for output.

Backport-to: 23.3
Backport-to: 24.0
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24855>
(cherry picked from commit b999e41250)
2024-03-10 01:51:17 +00:00
Mike Blumenkrantz
c54a222442 mesa: fix CopyTexImage format compatibility checks for ES
the ES spec imposes additional requirements for copy commands,
specifically that the formats have matching component sizes

the existing check used the driver's internal formats to check
for a match, which is broken since the spec requires the match be
between the passed internalFormat and the buffer's effective internal
format (i.e., this has no relation to what the driver supports)

fixes KHR-GLES3.copy_tex_image_conversions.forbidden* on a bunch of drivers

cc: mesa-stable

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28030>
(cherry picked from commit 2cd192f879)
2024-03-10 01:46:06 +00:00
Yiwei Zhang
5e8ca5d067 venus: fix ffb batch prepare for a corner case and avoid a memcpy UB
Batches must be ignored if batch count is zero, so all batch inspections
have to be gated behind batch count. For memcpy, it's UB if either src
or dst is NULL even when size is zero.

Side note:
- For original commit, this fixes just the memcpy UB
- For current codes, this fixes to not skip ffb batch prepare

Fixes: 493a3b5cda ("venus: refactor batch submission fixup")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28071>
(cherry picked from commit 8af267eb00)
2024-03-10 01:46:06 +00:00
David Heidelberg
4364f09974 intel/tools: avoid invalid time and file bits combination
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10780

Fixes: cc41603d6d ("intel/tools: new intel_sanitize_gpu tool")
Reported-by: Fabio Pedretti <pedretti.fabio@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28081>
(cherry picked from commit f5532f8bab)
2024-03-10 01:46:06 +00:00
Konstantin Seurer
8c84083a17 radv/rt: Fix raygen_imported condition
This can cause GPU hangs if the imported raygen shader is the first
shader of the library.

Fixes: 0f87d40 ("radv/rt: Skip compiling a traversal shader")
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
(cherry picked from commit 12c71ef847)
2024-03-10 01:46:06 +00:00
Eric Engestrom
ead9441e18 .pick_status.json: Mark a367cd4931 as denominated 2024-03-10 01:46:06 +00:00
Eric Engestrom
5ce5cfa3b6 .pick_status.json: Update to e1afffe7fa 2024-03-10 01:44:29 +00:00
Gert Wollny
79bd37189b zink/nir-to-spirv: Make sure sampleid for InterpolateAtSample is int
This fixes the validation error

  VUID-VkShaderModuleCreateInfo-pCode-08737

triggered by piglit:
  spec@arb_gpu_shader5@execution@built-in-functions@fs-interpolateatsample-block-array:

  GLSL.std.450 InterpolateAtSample: expected Sample to be 32-bit integer
    %47 = OpExtInst %float %1 InterpolateAtSample %45 %float_0

Fixes: 9f6be8effb
   zink: store and use alu types for ntv defs

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28043>
(cherry picked from commit b7d6d90dab)
2024-03-07 20:21:16 +00:00
Eric R. Smith
9ec4e8aa47 panfrost: protect alpha calculation from accessing non-existent component
We had a "Don't read out-of-bounds" sanity check for creating an alpha
when ATEST was needed, but that check happened only after we already
did a bi_extract(), which meant that the bi_extract could get into
trouble and assert() when there weren't enough components. Fixed by
re-arranging the calculation.

Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund>@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28045>
(cherry picked from commit 0e1862a2ab)
2024-03-07 20:21:16 +00:00
Eric Engestrom
933f7a68d1 .pick_status.json: Update to f3fe1f2f18 2024-03-07 20:21:16 +00:00
Friedrich Vock
eecce40e2a radv/rt: Fix frontface culling with emulated RT
We need to preserve the divisor's sign for front/backface detection to
work correctly.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28034>
(cherry picked from commit 7792ee1c15)
2024-03-07 20:21:16 +00:00
Konstantin Seurer
dfc52d165a radv/rt: Use doubles inside intersect_ray_amd_software_tri
Increasing precision lets us avoid duplicate hits on shared edges. The
previous biasing WA made a bunch of tests fail.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27243>
(cherry picked from commit f27a973283)
2024-03-07 20:21:16 +00:00
Kenneth Graunke
c968caaa69 iris: Fix tessellation evaluation shaders that use scratch
The code path for emitting tessellation commands when the TES needed
scratch space was failing to emit 3DSTATE_TE, and instead only emitting
3DSTATE_DS.  This meant that you could get HS and DS enabled with
tessellation itself turned off, which is utter nonsense and would
cause a GPU hang.

Alchemist and later takes a different path and don't take this bug,
but all earlier hardware would hit it.  Discovered while working on
compiler changes that caused a single piglit test to spill minorly,
and thus break entirely.

Fixes: 4256f7ed58 ("iris: Fill out scratch base address dynamically")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28032>
(cherry picked from commit 9e5fd49cbe)
2024-03-07 20:21:16 +00:00
Mike Blumenkrantz
14a15f8265 util/blitter: iterate samples in stencil_fallback
this matches handling in do_blits and fixes multisampled stencil blits

fixes (nv):
GTF-GL45.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27988>
(cherry picked from commit 2665badcfe)
2024-03-07 20:21:16 +00:00
Jesse Natalie
d12ea6f472 nir_lower_tex_shadow: For old-style shadows, use vec4(result, 0, 0, 1)
If the app requests a swizzle on the shadow sampler which doesn't just
return the red channel or literal 0s/1s, we'll crash attempting to build
the result vector. Use something that's probably valid.

Cc: mesa-stable
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28001>
(cherry picked from commit cda6877cb6)
2024-03-07 20:21:16 +00:00
Danylo Piliaiev
6fdb734b86 tu: Fix dynamic state not always being emitted
We precompile static state and count it as dynamic, so we have to
manually clear bitset that tells which dynamic state is set, in order to
make sure that future dynamic state will be emitted. The issue is that
framework remembers only a past REAL dynamic state and compares a new
dynamic state against it, and not against our static state masquaraded
as dynamic.

Example:
 - Set dynamic state S with value A
 - Bind pipeline with dynamic state S
 - Draw
 - Bind pipeline with static state S with value B
 - Draw
 - Set dynamic state S with value A
 - Bind pipeline with dynamic state S
 - Draw

Previously, at the last draw the dynamic state S was not dirty and
current dynamic state was equal to the past dynamic state, so
it was not emitted, while GPU used value B from static pipeline.

This fix, at the point of static pipeline binding, clears the
bitset which tells that dynamic state S was previously set.
This forces the next dynamic state to be re-emitted.

Fixes broken rendering in Arma 3, and probably some other
games running through DXVK.

Fixes: 97da0a7734
("tu: Rewrite to use common Vulkan dynamic state")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27961>
(cherry picked from commit a76fcebfc0)
2024-03-07 20:21:16 +00:00
Lionel Landwerlin
05eb8397cd anv/iris/blorp: use the right MOCS values for each engine
There are multiple problems currently :

   - blorp blitter commands overwrite the protection value coming from
     the driver
   - anv & iris are using render target MOCS for compute commands

Driver already have the ability to pass the MOCS values so we choose
to stick to that in this change. But now the driver need to select the
right MOCS depending on the engine the commands are going to run onto.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27956>
(cherry picked from commit 194afe8416)
2024-03-07 20:21:16 +00:00
Lionel Landwerlin
09073442c1 anv: fix incorrect ISL usage in buffer view creation
We need to use the usage parameter.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 64f20cec28 ("anv: prepare image/buffer views for non indirect descriptors")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27956>
(cherry picked from commit c40f14bb31)
2024-03-07 20:21:16 +00:00
Faith Ekstrand
2ee94a147c nvk: Return os_page_size for minMemoryMapAlignment
Fixes: 8017ac0e79 ("nvk: add some limits/features from binary driver.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28019>
(cherry picked from commit 33bf7ca710)
2024-03-07 20:21:16 +00:00
Gert Wollny
d92001d59c zink: use only ZINK_BIND_DESCRIPTOR
ZINK_BIND_RESOURCE_DESCRIPTOR and ZINK_BIND_SAMPLER_DESCRIPTOR are
always used together, so that we can replace these two values with
ZINK_BIND_DESCRIPTOR and use only one bit to represent the value.
With that we can also remove the aliasing of ZINK_BIND_DESCRIPTOR with
PIPE_BIND_CONST_BW.

Fixes:  13c6ad0038
    zink: use a single descriptor buffer for all non-bindless types

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28016>
(cherry picked from commit 8e239dda41)
2024-03-07 20:21:16 +00:00
Rhys Perry
8579909cb5 aco: don't combine linear and normal VGPR copies
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27697>
(cherry picked from commit f99443a68b)
2024-03-07 20:21:16 +00:00
Jonathan Gray
3426b29094 intel/dev: update DG2 device names
Ref: https://ark.intel.com/content/www/us/en/ark/products/codename/226095/products-formerly-alchemist.html
Ref: DG2 PRM, Volume 4: Configurations, Steppings and Device IDs
Fixes: 99354efe31 ("intel/dev: Add DG2 G12 PCI IDs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27944>
(cherry picked from commit 2777a4c692)
2024-03-07 20:21:15 +00:00
Rohan Garg
aa42cefb3c anv, blorp: Set COMPUTE_WALKER Message SIMD field
Fixes: d95bbf35 ('anv: Set COMPUTE_WALKER Message SIMD field')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27983>
(cherry picked from commit 731ffa0737)
2024-03-07 20:21:15 +00:00
qbojj
b98965d507 vulkan: Fix calculation of flags in vk_graphics_pipeline_state_fill
Fixes: 2b62d90158 ("vk/graphics_state: Support VK_KHR_maintenance5")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10705
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27929>
(cherry picked from commit 4b7f4724f8)
2024-03-07 20:21:15 +00:00
David Heidelberg
fa4eea1f12 ci/intel: split asus-cx9400-volteer into acer-cp514-2h-11{30,60}g7-volteer
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877>
(cherry picked from commit 1316854e74)
2024-03-07 20:21:15 +00:00
David Heidelberg
1880875820 ci/intel: move machine definition to the intel-tgl-skqp job
Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877>
(cherry picked from commit 861c123ba0)
2024-03-07 20:21:15 +00:00
David Heidelberg
01a3bd1da3 ci/intel: add acer-cp514-2h-11{30,60}g7-volteer
Originally asus-cx9400-volteer, but now we can choose machine regarding
to available CPU within.

Cc: mesa-stable
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27877>
(cherry picked from commit f9ba492647)
2024-03-07 20:21:15 +00:00