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Merge remote branch 'origin/7.8' into 7.8-gles

Browse Source
This commit is contained in:
Kristian Høgsberg 2010-05-14 15:05:02 -04:00
commit faa8c0ce8c
34 changed files with 241 additions and 232 deletions
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2
src/mesa/drivers/dri/i915/i915_tex_layout.c
View File

@ -484,7 +484,7 @@ i945_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree * mt,
case GL_TEXTURE_1D:
case GL_TEXTURE_2D:
case GL_TEXTURE_RECTANGLE_ARB:
i945_miptree_layout_2d(intel, mt, tiling);
i945_miptree_layout_2d(intel, mt, tiling, 1);
break;
default:
_mesa_problem(NULL, "Unexpected tex target in i945_miptree_layout()");

6
src/mesa/drivers/dri/i965/brw_clip.c
View File

@ -72,7 +72,7 @@ static void compile_clip_prog( struct brw_context *brw,
*/
c.header_position_offset = ATTR_SIZE;
if (intel->is_ironlake)
if (intel->gen == 5)
delta = 3 * REG_SIZE;
else
delta = REG_SIZE;
@ -85,7 +85,7 @@ static void compile_clip_prog( struct brw_context *brw,
c.nr_attrs = brw_count_bits(c.key.attrs);
if (intel->is_ironlake)
if (intel->gen == 5)
c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
else
c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */
@ -162,7 +162,7 @@ static void upload_clip_prog(struct brw_context *brw)
/* _NEW_TRANSFORM */
key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
if (intel->is_ironlake)
if (intel->gen == 5)
key.clip_mode = BRW_CLIPMODE_KERNEL_CLIP;
else
key.clip_mode = BRW_CLIPMODE_NORMAL;

4
src/mesa/drivers/dri/i965/brw_clip_state.c
View File

@ -102,10 +102,10 @@ clip_unit_create_from_key(struct brw_context *brw,
*/
assert(key->nr_urb_entries % 2 == 0);
/* Although up to 16 concurrent Clip threads are allowed on IGDNG,
/* Although up to 16 concurrent Clip threads are allowed on Ironlake,
* only 2 threads can output VUEs at a time.
*/
if (intel->is_ironlake)
if (intel->gen == 5)
clip.thread4.max_threads = 16 - 1;
else
clip.thread4.max_threads = 2 - 1;

2
src/mesa/drivers/dri/i965/brw_clip_tri.c
View File

@ -78,7 +78,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
for (j = 0; j < 3; j++) {
GLuint delta = c->nr_attrs*16 + 32;
if (intel->is_ironlake)
if (intel->gen == 5)
delta = c->nr_attrs * 16 + 32 * 3;
brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));

4
src/mesa/drivers/dri/i965/brw_clip_util.c
View File

@ -151,7 +151,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
for (i = 0; i < c->nr_attrs; i++) {
GLuint delta = i*16 + 32;
if (intel->is_ironlake)
if (intel->gen == 5)
delta = i * 16 + 32 * 3;
if (delta == c->offset[VERT_RESULT_EDGE]) {
@ -185,7 +185,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
if (i & 1) {
GLuint delta = i*16 + 32;
if (intel->is_ironlake)
if (intel->gen == 5)
delta = i * 16 + 32 * 3;
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));

4
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -151,7 +151,7 @@ GLboolean brwCreateContext( int api,
MIN2(ctx->Const.FragmentProgram.MaxNativeParameters,
ctx->Const.FragmentProgram.MaxEnvParams);
if (intel->is_ironlake || intel->is_g4x || intel->gen >= 6) {
if (intel->is_g4x || intel->gen >= 5) {
brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45;
brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45;
brw->has_surface_tile_offset = GL_TRUE;
@ -163,7 +163,7 @@ GLboolean brwCreateContext( int api,
}
/* WM maximum threads is number of EUs times number of threads per EU. */
if (intel->is_ironlake) {
if (intel->gen == 5) {
brw->urb.size = 1024;
brw->vs_max_threads = 72;
brw->wm_max_threads = 12 * 6;

10
src/mesa/drivers/dri/i965/brw_defines.h
View File

@ -674,12 +674,12 @@
#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
#define BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG 0
#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG 1
#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_IGDNG 2
#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG 3
#define BRW_SAMPLER_MESSAGE_SAMPLE_GEN5 0
#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5 1
#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_GEN5 2
#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5 3
/* for IGDNG only */
/* for GEN5 only */
#define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
#define BRW_SAMPLER_SIMD_MODE_SIMD8 1
#define BRW_SAMPLER_SIMD_MODE_SIMD16 2

4
src/mesa/drivers/dri/i965/brw_draw_upload.c
View File

@ -522,7 +522,7 @@ static void brw_emit_vertices(struct brw_context *brw)
OUT_RELOC(input->bo,
I915_GEM_DOMAIN_VERTEX, 0,
input->offset);
if (intel->is_ironlake || intel->gen >= 6) {
if (intel->gen >= 5) {
OUT_RELOC(input->bo,
I915_GEM_DOMAIN_VERTEX, 0,
input->bo->size - 1);
@ -565,7 +565,7 @@ static void brw_emit_vertices(struct brw_context *brw)
(0 << BRW_VE0_SRC_OFFSET_SHIFT));
}
if (intel->is_ironlake || intel->gen >= 6)
if (intel->gen >= 5)
OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
(comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
(comp2 << BRW_VE1_COMPONENT_2_SHIFT) |

154
src/mesa/drivers/dri/i965/brw_eu_emit.c
View File

@ -253,19 +253,19 @@ static void brw_set_math_message( struct brw_context *brw,
struct intel_context *intel = &brw->intel;
brw_set_src1(insn, brw_imm_d(0));
if (intel->is_ironlake) {
insn->bits3.math_igdng.function = function;
insn->bits3.math_igdng.int_type = integer_type;
insn->bits3.math_igdng.precision = low_precision;
insn->bits3.math_igdng.saturate = saturate;
insn->bits3.math_igdng.data_type = dataType;
insn->bits3.math_igdng.snapshot = 0;
insn->bits3.math_igdng.header_present = 0;
insn->bits3.math_igdng.response_length = response_length;
insn->bits3.math_igdng.msg_length = msg_length;
insn->bits3.math_igdng.end_of_thread = 0;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_MATH;
insn->bits2.send_igdng.end_of_thread = 0;
if (intel->gen == 5) {
insn->bits3.math_gen5.function = function;
insn->bits3.math_gen5.int_type = integer_type;
insn->bits3.math_gen5.precision = low_precision;
insn->bits3.math_gen5.saturate = saturate;
insn->bits3.math_gen5.data_type = dataType;
insn->bits3.math_gen5.snapshot = 0;
insn->bits3.math_gen5.header_present = 0;
insn->bits3.math_gen5.response_length = response_length;
insn->bits3.math_gen5.msg_length = msg_length;
insn->bits3.math_gen5.end_of_thread = 0;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_MATH;
insn->bits2.send_gen5.end_of_thread = 0;
} else {
insn->bits3.math.function = function;
insn->bits3.math.int_type = integer_type;
@ -293,18 +293,18 @@ static void brw_set_ff_sync_message( struct brw_context *brw,
{
brw_set_src1(insn, brw_imm_d(0));
insn->bits3.urb_igdng.opcode = 1;
insn->bits3.urb_igdng.offset = offset;
insn->bits3.urb_igdng.swizzle_control = swizzle_control;
insn->bits3.urb_igdng.allocate = allocate;
insn->bits3.urb_igdng.used = used;
insn->bits3.urb_igdng.complete = complete;
insn->bits3.urb_igdng.header_present = 1;
insn->bits3.urb_igdng.response_length = response_length;
insn->bits3.urb_igdng.msg_length = msg_length;
insn->bits3.urb_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
insn->bits3.urb_gen5.opcode = 1;
insn->bits3.urb_gen5.offset = offset;
insn->bits3.urb_gen5.swizzle_control = swizzle_control;
insn->bits3.urb_gen5.allocate = allocate;
insn->bits3.urb_gen5.used = used;
insn->bits3.urb_gen5.complete = complete;
insn->bits3.urb_gen5.header_present = 1;
insn->bits3.urb_gen5.response_length = response_length;
insn->bits3.urb_gen5.msg_length = msg_length;
insn->bits3.urb_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
}
static void brw_set_urb_message( struct brw_context *brw,
@ -321,17 +321,17 @@ static void brw_set_urb_message( struct brw_context *brw,
struct intel_context *intel = &brw->intel;
brw_set_src1(insn, brw_imm_d(0));
if (intel->is_ironlake || intel->gen >= 6) {
insn->bits3.urb_igdng.opcode = 0; /* ? */
insn->bits3.urb_igdng.offset = offset;
insn->bits3.urb_igdng.swizzle_control = swizzle_control;
insn->bits3.urb_igdng.allocate = allocate;
insn->bits3.urb_igdng.used = used; /* ? */
insn->bits3.urb_igdng.complete = complete;
insn->bits3.urb_igdng.header_present = 1;
insn->bits3.urb_igdng.response_length = response_length;
insn->bits3.urb_igdng.msg_length = msg_length;
insn->bits3.urb_igdng.end_of_thread = end_of_thread;
if (intel->gen >= 5) {
insn->bits3.urb_gen5.opcode = 0; /* ? */
insn->bits3.urb_gen5.offset = offset;
insn->bits3.urb_gen5.swizzle_control = swizzle_control;
insn->bits3.urb_gen5.allocate = allocate;
insn->bits3.urb_gen5.used = used; /* ? */
insn->bits3.urb_gen5.complete = complete;
insn->bits3.urb_gen5.header_present = 1;
insn->bits3.urb_gen5.response_length = response_length;
insn->bits3.urb_gen5.msg_length = msg_length;
insn->bits3.urb_gen5.end_of_thread = end_of_thread;
if (intel->gen >= 6) {
/* For SNB, the SFID bits moved to the condmod bits, and
* EOT stayed in bits3 above. Does the EOT bit setting
@ -339,8 +339,8 @@ static void brw_set_urb_message( struct brw_context *brw,
*/
insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_URB;
} else {
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
}
} else {
insn->bits3.urb.opcode = 0; /* ? */
@ -369,18 +369,18 @@ static void brw_set_dp_write_message( struct brw_context *brw,
struct intel_context *intel = &brw->intel;
brw_set_src1(insn, brw_imm_d(0));
if (intel->is_ironlake) {
insn->bits3.dp_write_igdng.binding_table_index = binding_table_index;
insn->bits3.dp_write_igdng.msg_control = msg_control;
insn->bits3.dp_write_igdng.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.dp_write_igdng.msg_type = msg_type;
insn->bits3.dp_write_igdng.send_commit_msg = 0;
insn->bits3.dp_write_igdng.header_present = 1;
insn->bits3.dp_write_igdng.response_length = response_length;
insn->bits3.dp_write_igdng.msg_length = msg_length;
insn->bits3.dp_write_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
if (intel->gen == 5) {
insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_write_gen5.msg_control = msg_control;
insn->bits3.dp_write_gen5.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.dp_write_gen5.msg_type = msg_type;
insn->bits3.dp_write_gen5.send_commit_msg = 0;
insn->bits3.dp_write_gen5.header_present = 1;
insn->bits3.dp_write_gen5.response_length = response_length;
insn->bits3.dp_write_gen5.msg_length = msg_length;
insn->bits3.dp_write_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
} else {
insn->bits3.dp_write.binding_table_index = binding_table_index;
insn->bits3.dp_write.msg_control = msg_control;
@ -407,18 +407,18 @@ static void brw_set_dp_read_message( struct brw_context *brw,
struct intel_context *intel = &brw->intel;
brw_set_src1(insn, brw_imm_d(0));
if (intel->is_ironlake) {
insn->bits3.dp_read_igdng.binding_table_index = binding_table_index;
insn->bits3.dp_read_igdng.msg_control = msg_control;
insn->bits3.dp_read_igdng.msg_type = msg_type;
insn->bits3.dp_read_igdng.target_cache = target_cache;
insn->bits3.dp_read_igdng.header_present = 1;
insn->bits3.dp_read_igdng.response_length = response_length;
insn->bits3.dp_read_igdng.msg_length = msg_length;
insn->bits3.dp_read_igdng.pad1 = 0;
insn->bits3.dp_read_igdng.end_of_thread = end_of_thread;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
insn->bits2.send_igdng.end_of_thread = end_of_thread;
if (intel->gen == 5) {
insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
insn->bits3.dp_read_gen5.msg_control = msg_control;
insn->bits3.dp_read_gen5.msg_type = msg_type;
insn->bits3.dp_read_gen5.target_cache = target_cache;
insn->bits3.dp_read_gen5.header_present = 1;
insn->bits3.dp_read_gen5.response_length = response_length;
insn->bits3.dp_read_gen5.msg_length = msg_length;
insn->bits3.dp_read_gen5.pad1 = 0;
insn->bits3.dp_read_gen5.end_of_thread = end_of_thread;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
insn->bits2.send_gen5.end_of_thread = end_of_thread;
} else {
insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/
insn->bits3.dp_read.msg_control = msg_control; /*8:11*/
@ -447,17 +447,17 @@ static void brw_set_sampler_message(struct brw_context *brw,
assert(eot == 0);
brw_set_src1(insn, brw_imm_d(0));
if (intel->is_ironlake) {
insn->bits3.sampler_igdng.binding_table_index = binding_table_index;
insn->bits3.sampler_igdng.sampler = sampler;
insn->bits3.sampler_igdng.msg_type = msg_type;
insn->bits3.sampler_igdng.simd_mode = simd_mode;
insn->bits3.sampler_igdng.header_present = header_present;
insn->bits3.sampler_igdng.response_length = response_length;
insn->bits3.sampler_igdng.msg_length = msg_length;
insn->bits3.sampler_igdng.end_of_thread = eot;
insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_igdng.end_of_thread = eot;
if (intel->gen == 5) {
insn->bits3.sampler_gen5.binding_table_index = binding_table_index;
insn->bits3.sampler_gen5.sampler = sampler;
insn->bits3.sampler_gen5.msg_type = msg_type;
insn->bits3.sampler_gen5.simd_mode = simd_mode;
insn->bits3.sampler_gen5.header_present = header_present;
insn->bits3.sampler_gen5.response_length = response_length;
insn->bits3.sampler_gen5.msg_length = msg_length;
insn->bits3.sampler_gen5.end_of_thread = eot;
insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER;
insn->bits2.send_gen5.end_of_thread = eot;
} else if (intel->is_g4x) {
insn->bits3.sampler_g4x.binding_table_index = binding_table_index;
insn->bits3.sampler_g4x.sampler = sampler;
@ -663,7 +663,7 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
struct brw_instruction *insn;
GLuint br = 1;
if (intel->is_ironlake)
if (intel->gen == 5)
br = 2;
if (p->single_program_flow) {
@ -705,7 +705,7 @@ void brw_ENDIF(struct brw_compile *p,
struct intel_context *intel = &p->brw->intel;
GLuint br = 1;
if (intel->is_ironlake)
if (intel->gen == 5)
br = 2;
if (p->single_program_flow) {
@ -820,7 +820,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *insn;
GLuint br = 1;
if (intel->is_ironlake)
if (intel->gen == 5)
br = 2;
if (p->single_program_flow)
@ -864,7 +864,7 @@ void brw_land_fwd_jump(struct brw_compile *p,
struct brw_instruction *landing = &p->store[p->nr_insn];
GLuint jmpi = 1;
if (intel->is_ironlake)
if (intel->gen == 5)
jmpi = 2;
assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);

2
src/mesa/drivers/dri/i965/brw_gs.c
View File

@ -60,7 +60,7 @@ static void compile_gs_prog( struct brw_context *brw,
*/
c.nr_attrs = brw_count_bits(c.key.attrs);
if (intel->is_ironlake)
if (intel->gen == 5)
c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */
else
c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */

2
src/mesa/drivers/dri/i965/brw_gs_state.c
View File

@ -98,7 +98,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key)
else
gs.thread4.max_threads = 0;
if (intel->is_ironlake)
if (intel->gen == 5)
gs.thread4.rendering_enable = 1;
if (INTEL_DEBUG & DEBUG_STATS)

8
src/mesa/drivers/dri/i965/brw_misc_state.c
View File

@ -248,7 +248,7 @@ static void emit_depthbuffer(struct brw_context *brw)
if (intel->gen >= 6)
len = 7;
else if (intel->is_g4x || intel->is_ironlake)
else if (intel->is_g4x || intel->gen == 5)
len = 6;
else
len = 5;
@ -262,7 +262,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(0);
if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6)
if (intel->is_g4x || intel->gen >= 5)
OUT_BATCH(0);
if (intel->gen >= 6)
@ -306,7 +306,7 @@ static void emit_depthbuffer(struct brw_context *brw)
((region->height - 1) << 19));
OUT_BATCH(0);
if (intel->is_g4x || intel->is_ironlake || intel->gen >= 6)
if (intel->is_g4x || intel->gen >= 5)
OUT_BATCH(0);
if (intel->gen >= 6)
@ -608,7 +608,7 @@ static void upload_state_base_address( struct brw_context *brw )
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
ADVANCE_BATCH();
} else if (intel->is_ironlake) {
} else if (intel->gen == 5) {
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */

34
src/mesa/drivers/dri/i965/brw_program.c
View File

@ -34,6 +34,7 @@
#include "shader/prog_parameter.h"
#include "shader/program.h"
#include "shader/programopt.h"
#include "shader/shader_api.h"
#include "tnl/tnl.h"
#include "brw_context.h"
@ -119,12 +120,28 @@ static GLboolean brwIsProgramNative( GLcontext *ctx,
return GL_TRUE;
}
static void
shader_error(GLcontext *ctx, struct gl_program *prog, const char *msg)
{
struct gl_shader_program *shader;
shader = _mesa_lookup_shader_program(ctx, prog->Id);
if (shader) {
if (shader->InfoLog) {
free(shader->InfoLog);
}
shader->InfoLog = _mesa_strdup(msg);
shader->LinkStatus = GL_FALSE;
}
}
static GLboolean brwProgramStringNotify( GLcontext *ctx,
GLenum target,
struct gl_program *prog )
{
struct brw_context *brw = brw_context(ctx);
int i;
if (target == GL_FRAGMENT_PROGRAM_ARB) {
struct gl_fragment_program *fprog = (struct gl_fragment_program *) prog;
@ -160,7 +177,22 @@ static GLboolean brwProgramStringNotify( GLcontext *ctx,
_tnl_program_string(ctx, target, prog);
}
/* XXX check if program is legal, within limits */
/* Reject programs with subroutines, which are totally broken at the moment
* (all program flows return when any program flow returns, and
* the VS also hangs if a function call calls a function.
*
* See piglit glsl-{vs,fs}-functions-[23] tests.
*/
for (i = 0; i < prog->NumInstructions; i++) {
if (prog->Instructions[i].Opcode == OPCODE_CAL) {
shader_error(ctx, prog,
"i965 driver doesn't yet support uninlined function "
"calls. Move to using a single return statement at "
"the end of the function to work around it.");
return GL_FALSE;
}
}
return GL_TRUE;
}

4
src/mesa/drivers/dri/i965/brw_sf_emit.c
View File

@ -162,7 +162,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c )
if (c->key.primitive == SF_UNFILLED_TRIS)
return;
if (intel->is_ironlake)
if (intel->gen == 5)
jmpi = 2;
brw_push_insn_state(p);
@ -201,7 +201,7 @@ static void do_flatshade_line( struct brw_sf_compile *c )
if (c->key.primitive == SF_UNFILLED_TRIS)
return;
if (intel->is_ironlake)
if (intel->gen == 5)
jmpi = 2;
brw_push_insn_state(p);

19
src/mesa/drivers/dri/i965/brw_sf_state.c
View File

@ -76,7 +76,20 @@ static void upload_sf_vp(struct brw_context *brw)
* Note that the hardware's coordinates are inclusive, while Mesa's min is
* inclusive but max is exclusive.
*/
if (render_to_fbo) {
if (ctx->DrawBuffer->_Xmin == ctx->DrawBuffer->_Xmax ||
ctx->DrawBuffer->_Ymin == ctx->DrawBuffer->_Ymax) {
/* If the scissor was out of bounds and got clamped to 0
* width/height at the bounds, the subtraction of 1 from
* maximums could produce a negative number and thus not clip
* anything. Instead, just provide a min > max scissor inside
* the bounds, which produces the expected no rendering.
*/
sfv.scissor.xmin = 1;
sfv.scissor.xmax = 0;
sfv.scissor.ymin = 1;
sfv.scissor.ymax = 0;
} else if (render_to_fbo) {
/* texmemory: Y=0=bottom */
sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
@ -177,7 +190,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
sf.thread3.dispatch_grf_start_reg = 3;
if (intel->is_ironlake)
if (intel->gen == 5)
sf.thread3.urb_entry_read_offset = 3;
else
sf.thread3.urb_entry_read_offset = 1;
@ -190,7 +203,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
/* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or
* 48 (Ironlake) threads.
*/
if (intel->is_ironlake)
if (intel->gen == 5)
chipset_max_threads = 48;
else
chipset_max_threads = 24;

18
src/mesa/drivers/dri/i965/brw_structs.h
View File

@ -925,7 +925,7 @@ struct brw_gs_unit_state
struct
{
GLuint pad0:8;
GLuint rendering_enable:1; /* for IGDNG */
GLuint rendering_enable:1; /* for Ironlake */
GLuint pad4:1;
GLuint stats_enable:1;
GLuint nr_urb_entries:7;
@ -1035,7 +1035,7 @@ struct brw_wm_unit_state
GLfloat global_depth_offset_constant;
GLfloat global_depth_offset_scale;
/* for IGDNG only */
/* for Ironlake only */
struct {
GLuint pad0:1;
GLuint grf_reg_count_1:3;
@ -1448,7 +1448,7 @@ struct brw_instruction
GLuint end_of_thread:1;
GLuint pad1:1;
GLuint sfid:4;
} send_igdng; /* for IGDNG only */
} send_gen5; /* for Ironlake only */
} bits2;
@ -1549,7 +1549,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} math_igdng;
} math_gen5;
struct {
GLuint binding_table_index:8;
@ -1585,7 +1585,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} sampler_igdng;
} sampler_gen5;
struct brw_urb_immediate urb;
@ -1603,7 +1603,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} urb_igdng;
} urb_gen5;
struct {
GLuint binding_table_index:8;
@ -1628,7 +1628,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_read_igdng;
} dp_read_gen5;
struct {
GLuint binding_table_index:8;
@ -1655,7 +1655,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_write_igdng;
} dp_write_gen5;
struct {
GLuint pad:16;
@ -1673,7 +1673,7 @@ struct brw_instruction
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} generic_igdng;
} generic_gen5;
GLint d;
GLuint ud;

82
src/mesa/drivers/dri/i965/brw_tex_layout.c
View File

@ -48,77 +48,31 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
switch (mt->target) {
case GL_TEXTURE_CUBE_MAP:
if (intel->is_ironlake) {
GLuint align_h = 2, align_w = 4;
if (intel->gen == 5) {
GLuint align_h = 2;
GLuint level;
GLuint x = 0;
GLuint y = 0;
GLuint width = mt->width0;
GLuint height = mt->height0;
GLuint qpitch = 0;
GLuint y_pitch = 0;
int h0, h1, q;
mt->pitch = mt->width0;
intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
y_pitch = ALIGN(height, align_h);
/* On Ironlake, cube maps are finally represented as just a series
* of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
* by a pitch of qpitch rows, where qpitch is defined by the equation
* given in Volume 1 of the BSpec.
*/
h0 = ALIGN(mt->height0, align_h);
h1 = ALIGN(minify(h0), align_h);
qpitch = (h0 + h1 + 11 * align_h);
if (mt->compressed)
qpitch /= 4;
if (mt->compressed) {
mt->pitch = ALIGN(mt->width0, align_w);
}
if (mt->first_level != mt->last_level) {
GLuint mip1_width;
if (mt->compressed) {
mip1_width = ALIGN(minify(mt->width0), align_w)
+ ALIGN(minify(minify(mt->width0)), align_w);
} else {
mip1_width = ALIGN(minify(mt->width0), align_w)
+ minify(minify(mt->width0));
}
if (mip1_width > mt->pitch) {
mt->pitch = mip1_width;
}
}
mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
if (mt->compressed) {
qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4;
mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
} else {
qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h);
mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
}
i945_miptree_layout_2d(intel, mt, tiling, 6);
for (level = mt->first_level; level <= mt->last_level; level++) {
GLuint img_height;
GLuint nr_images = 6;
GLuint q = 0;
intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
height, 1);
for (q = 0; q < nr_images; q++)
intel_miptree_set_image_offset(mt, level, q,
x, y + q * qpitch);
if (mt->compressed)
img_height = MAX2(1, height/4);
else
img_height = ALIGN(height, align_h);
if (level == mt->first_level + 1) {
x += ALIGN(width, align_w);
for (q = 0; q < 6; q++) {
intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
}
else {
y += img_height;
}
width = minify(width);
height = minify(height);
}
mt->total_height = qpitch * 6;
break;
}
@ -208,7 +162,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
}
default:
i945_miptree_layout_2d(intel, mt, tiling);
i945_miptree_layout_2d(intel, mt, tiling, 1);
break;
}
DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,

2
src/mesa/drivers/dri/i965/brw_urb.c
View File

@ -148,7 +148,7 @@ static void recalculate_urb_fence( struct brw_context *brw )
brw->urb.constrained = 0;
if (intel->is_ironlake) {
if (intel->gen == 5) {
brw->urb.nr_vs_entries = 128;
brw->urb.nr_sf_entries = 48;
if (check_urb_layout(brw)) {

8
src/mesa/drivers/dri/i965/brw_vs_emit.c
View File

@ -182,7 +182,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
if (intel->gen >= 6)
mrf = 6;
else if (intel->is_ironlake)
else if (intel->gen == 5)
mrf = 8;
else
mrf = 4;
@ -283,7 +283,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
if (intel->gen >= 6)
c->prog_data.urb_entry_size = (attributes_in_vue + 4 + 7) / 8;
else if (intel->is_ironlake)
else if (intel->gen == 5)
c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4;
else
c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
@ -1288,7 +1288,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
brw_MOV(p, offset(m0, 2), pos);
brw_MOV(p, offset(m0, 5), pos);
len_vertex_header = 4;
} else if (intel->is_ironlake) {
} else if (intel->gen == 5) {
/* There are 20 DWs (D0-D19) in VUE header on Ironlake:
* dword 0-3 (m1) of the header is indices, point width, clip flags.
* dword 4-7 (m2) is the ndc position (set above)
@ -1710,7 +1710,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
loop_depth--;
if (intel->is_ironlake)
if (intel->gen == 5)
br = 2;
inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);

6
src/mesa/drivers/dri/i965/brw_vs_state.c
View File

@ -98,7 +98,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
*/
vs.thread1.single_program_flow = 0;
if (intel->is_ironlake)
if (intel->gen == 5)
vs.thread1.binding_table_entry_count = 0; /* hardware requirement */
else
vs.thread1.binding_table_entry_count = key->nr_surfaces;
@ -109,7 +109,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
vs.thread3.urb_entry_read_offset = 0;
vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
if (intel->is_ironlake) {
if (intel->gen == 5) {
switch (key->nr_urb_entries) {
case 8:
case 12:
@ -150,7 +150,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key)
/* No samplers for ARB_vp programs:
*/
/* It has to be set to 0 for IGDNG
/* It has to be set to 0 for Ironlake
*/
vs.vs5.sampler_count = 0;

18
src/mesa/drivers/dri/i965/brw_wm_emit.c
View File

@ -898,7 +898,7 @@ void emit_tex(struct brw_wm_compile *c,
}
/* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
if (!intel->is_ironlake && c->dispatch_width == 8)
if (intel->gen < 5 && c->dispatch_width == 8)
nr_texcoords = 3;
/* For shadow comparisons, we have to supply u,v,r. */
@ -916,7 +916,7 @@ void emit_tex(struct brw_wm_compile *c,
/* Fill in the shadow comparison reference value. */
if (shadow) {
if (intel->is_ironlake) {
if (intel->gen == 5) {
/* Fill in the cube map array index value. */
brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0));
cur_mrf += mrf_per_channel;
@ -929,11 +929,11 @@ void emit_tex(struct brw_wm_compile *c,
cur_mrf += mrf_per_channel;
}
if (intel->is_ironlake) {
if (intel->gen == 5) {
if (shadow)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG;
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
else
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG;
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
} else {
/* Note that G45 and older determines shadow compare and dispatch width
* from message length for most messages.
@ -981,16 +981,16 @@ void emit_txb(struct brw_wm_compile *c,
* undefined, and trust the execution mask to keep the undefined pixels
* from mattering.
*/
if (c->dispatch_width == 16 || !intel->is_ironlake) {
if (intel->is_ironlake)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG;
if (c->dispatch_width == 16 || intel->gen < 5) {
if (intel->gen == 5)
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
else
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
mrf_per_channel = 2;
dst_retyped = retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW);
response_length = 8;
} else {
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG;
msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
mrf_per_channel = 1;
dst_retyped = retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW);
response_length = 4;

2
src/mesa/drivers/dri/i965/brw_wm_glsl.c
View File

@ -2006,7 +2006,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
struct brw_instruction *inst0, *inst1;
GLuint br = 1;
if (intel->is_ironlake)
if (intel->gen == 5)
br = 2;
assert(loop_depth > 0);

4
src/mesa/drivers/dri/i965/brw_wm_state.c
View File

@ -137,7 +137,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
wm.thread1.depth_coef_urb_read_offset = 1;
wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
if (intel->is_ironlake)
if (intel->gen == 5)
wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
else
wm.thread1.binding_table_entry_count = key->nr_surfaces;
@ -157,7 +157,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
if (intel->is_ironlake)
if (intel->gen == 5)
wm.wm4.sampler_count = 0; /* hardware requirement */
else
wm.wm4.sampler_count = (key->sampler_count + 1) / 4;

2
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -588,7 +588,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
tile_base = ((key.draw_y / 32) * (32 * pitch));
tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
}
assert(intel->is_g4x || (tile_x == 0 && tile_y == 0));
assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
assert(tile_x % 4 == 0);
assert(tile_y % 2 == 0);
/* Note that the low bits of these fields are missing, so

4
src/mesa/drivers/dri/intel/intel_chipset.h
View File

@ -93,7 +93,7 @@
#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
#define IS_IGDNG(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
devid == PCI_CHIP_E7221_G || \
@ -118,7 +118,7 @@
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
IS_IGDNG(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid))
#define IS_9XX(devid) (IS_915(devid) || \

25
src/mesa/drivers/dri/intel/intel_context.c
View File

@ -159,10 +159,10 @@ intelGetString(GLcontext * ctx, GLenum name)
chipset = "Intel(R) B43";
break;
case PCI_CHIP_ILD_G:
chipset = "Intel(R) IGDNG_D";
chipset = "Intel(R) Ironlake Desktop";
break;
case PCI_CHIP_ILM_G:
chipset = "Intel(R) IGDNG_M";
chipset = "Intel(R) Ironlake Mobile";
break;
default:
chipset = "Unknown Intel Chipset";
@ -362,7 +362,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
if (buffers[i].attachment == __DRI_BUFFER_DEPTH)
depth_region = region;
intel_renderbuffer_set_region(rb, region);
intel_renderbuffer_set_region(intel, rb, region);
intel_region_release(&region);
if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
@ -374,7 +374,7 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
continue;
intel_region_reference(&stencil_region, region);
intel_renderbuffer_set_region(rb, stencil_region);
intel_renderbuffer_set_region(intel, rb, stencil_region);
intel_region_release(&stencil_region);
}
}
@ -615,8 +615,16 @@ intelInitContext(struct intel_context *intel,
intel->gen = 6;
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
} else if (IS_GEN5(intel->intelScreen->deviceID)) {
intel->gen = 5;
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
} else if (IS_965(intel->intelScreen->deviceID)) {
intel->gen = 4;
if (IS_G4X(intel->intelScreen->deviceID)) {
intel->has_luminance_srgb = GL_TRUE;
intel->is_g4x = GL_TRUE;
}
} else if (IS_9XX(intel->intelScreen->deviceID)) {
intel->gen = 3;
if (IS_945(intel->intelScreen->deviceID)) {
@ -626,15 +634,6 @@ intelInitContext(struct intel_context *intel,
intel->gen = 2;
}
if (IS_IGDNG(intel->intelScreen->deviceID)) {
intel->is_ironlake = GL_TRUE;
intel->needs_ff_sync = GL_TRUE;
intel->has_luminance_srgb = GL_TRUE;
} else if (IS_G4X(intel->intelScreen->deviceID)) {
intel->has_luminance_srgb = GL_TRUE;
intel->is_g4x = GL_TRUE;
}
driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
intel->driScreen->myNum,
(intel->gen >= 4) ? "i965" : "i915");

1
src/mesa/drivers/dri/intel/intel_context.h
View File

@ -142,7 +142,6 @@ struct intel_context
*/
int gen;
GLboolean needs_ff_sync;
GLboolean is_ironlake;
GLboolean is_g4x;
GLboolean is_945;
GLboolean has_luminance_srgb;

13
src/mesa/drivers/dri/intel/intel_fbo.c
View File

@ -42,7 +42,9 @@
#include "intel_fbo.h"
#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#ifndef I915
#include "brw_state.h"
#endif
#define FILE_DEBUG_FLAG DEBUG_FBO
@ -280,7 +282,8 @@ intel_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
void
intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
intel_renderbuffer_set_region(struct intel_context *intel,
struct intel_renderbuffer *rb,
struct intel_region *region)
{
struct intel_region *old;
@ -288,6 +291,12 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb,
old = rb->region;
rb->region = NULL;
intel_region_reference(&rb->region, region);
#ifndef I915
if (old) {
brw_state_cache_bo_delete(&brw_context(&intel->ctx)->surface_cache,
old->buffer);
}
#endif
intel_region_release(&old);
}

3
src/mesa/drivers/dri/intel/intel_fbo.h
View File

@ -82,7 +82,8 @@ intel_get_renderbuffer(struct gl_framebuffer *fb, int attIndex)
extern void
intel_renderbuffer_set_region(struct intel_renderbuffer *irb,
intel_renderbuffer_set_region(struct intel_context *intel,
struct intel_renderbuffer *irb,
struct intel_region *region);

7
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
View File

@ -117,17 +117,16 @@ intel_miptree_create(struct intel_context *intel,
GLboolean expect_accelerated_upload)
{
struct intel_mipmap_tree *mt;
uint32_t tiling;
uint32_t tiling = I915_TILING_NONE;
if (intel->use_texture_tiling && compress_byte == 0) {
if (intel->gen >= 4 &&
(base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL_EXT))
tiling = I915_TILING_Y;
else
else if (width0 >= 64)
tiling = I915_TILING_X;
} else
tiling = I915_TILING_NONE;
}
mt = intel_miptree_create_internal(intel, target, internal_format,
first_level, last_level, width0,

2
src/mesa/drivers/dri/intel/intel_pixel_draw.c
View File

@ -167,7 +167,7 @@ intel_stencil_drawpixels(GLcontext * ctx,
irb = intel_create_renderbuffer(MESA_FORMAT_ARGB8888);
irb->Base.Width = depth_irb->Base.Width;
irb->Base.Height = depth_irb->Base.Height;
intel_renderbuffer_set_region(irb, depth_irb->region);
intel_renderbuffer_set_region(intel, irb, depth_irb->region);
/* Create a name for our renderbuffer, which lets us use other mesa
* rb functions for convenience.

6
src/mesa/drivers/dri/intel/intel_tex_layout.c
View File

@ -63,9 +63,9 @@ void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *
}
}
void i945_miptree_layout_2d( struct intel_context *intel,
void i945_miptree_layout_2d(struct intel_context *intel,
struct intel_mipmap_tree *mt,
uint32_t tiling )
uint32_t tiling, int nr_images)
{
GLuint align_h = 2, align_w = 4;
GLuint level;
@ -111,7 +111,7 @@ void i945_miptree_layout_2d( struct intel_context *intel,
for ( level = mt->first_level ; level <= mt->last_level ; level++ ) {
GLuint img_height;
intel_miptree_set_level_info(mt, level, 1, x, y, width,
intel_miptree_set_level_info(mt, level, nr_images, x, y, width,
height, 1);
if (mt->compressed)

2
src/mesa/drivers/dri/intel/intel_tex_layout.h
View File

@ -40,5 +40,5 @@ static INLINE GLuint minify( GLuint d )
extern void i945_miptree_layout_2d(struct intel_context *intel,
struct intel_mipmap_tree *mt,
uint32_t tiling);
uint32_t tiling, int nr_images);
extern void intel_get_texture_alignment_unit(GLenum, GLuint *, GLuint *);

5
src/mesa/shader/slang/slang_link.c
View File

@ -921,7 +921,10 @@ _slang_link(GLcontext *ctx,
if (!vertNotify || !fragNotify) {
/* driver rejected one/both of the vertex/fragment programs */
link_error(shProg, "Vertex and/or fragment program rejected by driver\n");
if (!shProg->InfoLog) {
link_error(shProg,
"Vertex and/or fragment program rejected by driver\n");
}
}
else {
shProg->LinkStatus = (shProg->VertexProgram || shProg->FragmentProgram);