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freedreno/registers: Start adding stuff for a7xx

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Start adding the bits needed for userspace.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>
This commit is contained in:
Rob Clark 2022-08-03 07:56:35 -07:00 committed by Marge Bot
parent b90d4a0701
commit f011189642
3 changed files with 69 additions and 17 deletions
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2
src/freedreno/.gitlab-ci/reference/afuc_test.asm
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@ -225,7 +225,7 @@ CP_EVENT_WRITE_CFL:
UNKN90:
CP_EVENT_WRITE_ZPD:
CP_CONTEXT_REG_BUNCH:
CP_WAIT_IB_PFD_COMPLETE:
UNKN93:
CP_CONTEXT_UPDATE:
CP_SET_PROTECTED_MODE:
UNKN96:

37
src/freedreno/registers/adreno/a6xx.xml
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@ -3706,30 +3706,57 @@ to upconvert to 32b float internally?
</reg32>
<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean"/> <!-- never used by blob -->
<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2">
<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX">
<!-- TODO: have test cases with either 0x3 or 0x7 -->
</reg32>
<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
<reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX">
<!-- TODO: have test cases with either 0x3 or 0x7 -->
</reg32>
<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX">
<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
<!-- SAMPLEID is loaded into a half-precision register: -->
<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
<bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
<reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX">
<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
<!-- SAMPLEID is loaded into a half-precision register: -->
<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
<bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG" variants="A6XX">
<!-- register loaded with position (bary.f) -->
<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
<reg32 offset="0xa9c9" name="HLSQ_CONTROL_3_REG" variants="A7XX">
<!-- register loaded with position (bary.f) -->
<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG" variants="A6XX">
<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
<reg32 offset="0xa9ca" name="HLSQ_CONTROL_4_REG" variants="A7XX">
<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG" variants="A6XX">
<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
<bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xa9cb" name="HLSQ_CONTROL_5_REG" variants="A7XX">
<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
<bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
</reg32>

47
src/freedreno/registers/adreno/adreno_pm4.xml
View File

@ -271,7 +271,11 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<doc>wait until a read completes</doc>
<value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
<doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
<value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
<!--
NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and
recycled for something new on a7xx
-->
<value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
<doc>register read/modify/write</doc>
<value name="CP_REG_RMW" value="0x21"/>
<doc>Set binning configuration registers</doc>
@ -458,7 +462,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/>
<!-- for a6xx -->
<doc>Tells CP the current mode of GPU operation</doc>
<value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
<value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
<doc>Instruct CP to set a few internal CP registers</doc>
<value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
<!--
@ -508,7 +512,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
packets w/ ENABLE_MASK & 0x6 to execute immediately
-->
<value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
<value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
<!--
Seems like there are now separate blocks of state for VS vs FS/CS
@ -524,15 +528,15 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
CL_KERNEL_WORK_GROUP_SIZE)
-->
<value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
<value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
<value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
<value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
<!--
Note: For IBO state (Image/SSBOs) which have shared state across
shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
interchangable.
-->
<value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
<value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
<!-- internal packets: -->
<value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
@ -569,7 +573,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
</doc>
<value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/>
<!-- Note, kgsl calls this CP_SET_AMBLE: -->
<value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
<value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX-"/>
<!--
Seems to always have the payload:
@ -604,14 +608,23 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
technique of just repeating the CP_INDIRECT_BUFFER calls and
"unrolling" the loop.
</doc>
<value name="CP_START_BIN" value="0x50" variants="A6XX"/>
<value name="CP_END_BIN" value="0x51" variants="A6XX"/>
<value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
<value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
<doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
<value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/>
<value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
<value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/>
<!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
<value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
<!-- new on a7xx, currently unknown: -->
<value name="CP_UNK15" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
<value name="CP_UNK16" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 -->
<value name="CP_UNK18" value="0x18" variants="A7XX-"/> <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?-->
<value name="CP_UNK1B" value="0x1b" variants="A7XX-"/> <!-- payload 1 or 2 dwords -->
<value name="CP_UNK49" value="0x49" variants="A7XX-"/> <!-- payload 4 dwords, last two address of something -->
</enum>
@ -1097,6 +1110,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<reg32 offset="6" name="6">
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
</reg32>
<!--
a7xx adds a few more addresses to the end of the pkt
-->
<reg64 offset="7" name="7"/>
<reg64 offset="9" name="9"/>
</domain>
<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
@ -1939,10 +1957,17 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</reg32>
</domain>
<domain name="CP_WAIT_TIMESTAMP" width="32">
<reg32 offset="0" name="0">
</reg32>
<reg64 offset="1" name="ADDR" type="address"/>
<reg32 offset="3" name="TIMESTAMP" type="uint"/>
</domain>
<domain name="CP_THREAD_CONTROL" width="32">
<enum name="cp_thread">
<value name="CP_SET_THREAD_BR" value="1"/>
<value name="CP_SET_THREAD_BV" value="2"/>
<value name="CP_SET_THREAD_BR" value="1"/> <!-- Render -->
<value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility -->
<value name="CP_SET_THREAD_BOTH" value="3"/>
</enum>
<reg32 offset="0" name="0">