intel/brw: Use REG_CLASS_COUNT

Fixes: 5d87f41a54 ("intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30314>
(cherry picked from commit 5e24c21625)
This commit is contained in:
Matt Turner 2024-07-22 19:35:13 -04:00 committed by Eric Engestrom
parent 7ebc7983d4
commit e4bceffb5f
3 changed files with 4 additions and 4 deletions

View File

@ -1454,7 +1454,7 @@
"description": "intel/brw: Use REG_CLASS_COUNT",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "5d87f41a546b26650b15fb33c5f1153aa041a037",
"notes": null

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@ -47,6 +47,8 @@ struct shader_info;
struct nir_shader_compiler_options;
typedef struct nir_shader nir_shader;
#define REG_CLASS_COUNT 20
struct brw_compiler {
const struct intel_device_info *devinfo;
@ -64,7 +66,7 @@ struct brw_compiler {
* Array of the ra classes for the unaligned contiguous register
* block sizes used, indexed by register size.
*/
struct ra_class *classes[16];
struct ra_class *classes[REG_CLASS_COUNT];
} fs_reg_set;
void (*shader_debug_log)(void *, unsigned *id, const char *str, ...) PRINTFLIKE(3, 4);

View File

@ -34,8 +34,6 @@
using namespace brw;
#define REG_CLASS_COUNT 20
static void
assign_reg(const struct intel_device_info *devinfo,
unsigned *reg_hw_locations, fs_reg *reg)