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anv, iris: add missing CS_STALL bit for GPGPU texture invalidation

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The BSpec page "Flush Types" (46213) says the following about the Tex
Invalidate bit:

  "Requires stall bit ([20] of DW) set for all GPGPU Workloads."

For newer platforms, this is documented in the description of the
texture invalidation bit in the PIPE_CONTROL page (56551):

  "CS Stall bit in PIPE_CONTROL command must be always set for GPGPU
   workloads when Texture Cache Invalidation Enable bit is set"

Iris had it only for GFX_VER 9 and 11, while Anv had it missing for
everything.

Please notice that this patch includes a revert of 397e728ef4.

Fixes: 397e728ef4 ("iris: Drop GPGPU Tex Invalidate restriction for TGL+")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28608>
(cherry picked from commit cf7e1f3817)
This commit is contained in:
Paulo Zanoni 2024-04-05 12:49:53 -07:00 committed by Eric Engestrom
parent c73e830dc9
commit dac8689fc3
3 changed files with 17 additions and 5 deletions
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2
.pick_status.json
View File

@ -604,7 +604,7 @@
"description": "anv, iris: add missing CS_STALL bit for GPGPU texture invalidation", "description": "anv, iris: add missing CS_STALL bit for GPGPU texture invalidation",
"nominated": true, "nominated": true,
"nomination_type": 1, "nomination_type": 1,
"resolution": 0, "resolution": 1,
"main_sha": null, "main_sha": null,
"because_sha": "397e728ef4f1247c0c2d11bf8516763b2a3088ff", "because_sha": "397e728ef4f1247c0c2d11bf8516763b2a3088ff",
"notes": null "notes": null

10
src/gallium/drivers/iris/iris_state.c
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@ -9537,10 +9537,12 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
/* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
if (IS_COMPUTE_PIPELINE(batch)) { if (IS_COMPUTE_PIPELINE(batch)) {
if ((GFX_VER == 9 || GFX_VER == 11) && if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) {
(flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { /* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for
/* Project: SKL, ICL / Argument: Tex Invalidate * PIPE_CONTROL, Flush Types:
* "Requires stall bit ([20] of DW) set for all GPGPU Workloads." * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
* For newer platforms this is documented in the PIPE_CONTROL
* instruction page.
*/ */
flags |= PIPE_CONTROL_CS_STALL; flags |= PIPE_CONTROL_CS_STALL;
} }

10
src/intel/vulkan/genX_cmd_buffer.c
View File

@ -2928,6 +2928,16 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch,
}; };
} }
/* SKL PRMs, Volume 7: 3D-Media-GPGPU, Programming Restrictions for
* PIPE_CONTROL, Flush Types:
* "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
* For newer platforms this is documented in the PIPE_CONTROL instruction
* page.
*/
if (current_pipeline == GPGPU &&
(bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT))
bits |= ANV_PIPE_CS_STALL_BIT;
#if INTEL_NEEDS_WA_1409600907 #if INTEL_NEEDS_WA_1409600907
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set. * be set with any PIPE_CONTROL with Depth Flush Enable bit set.