mirrors/mesa
0
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2024-12-02 22:54:05 +08:00
Code Issues Packages Projects Releases Wiki Activity

radeonsi: replace nonir,noir,noasm,preoptir options with new reworked options

Browse Source 
New options depending on what you want to print:
- initnir  = initial NIR of shader CSOs
- nir      = final NIR of variants after all lowering
- initllvm = LLVM IR before optimizations
- llvm     = final LLVM IR
- asm      = asm

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21860>
This commit is contained in:
Marek Olšák 2023-03-10 21:55:08 -05:00 committed by Marge Bot
parent c3df9973a3
commit d76bb15c51
7 changed files with 60 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/gallium/drivers/radeonsi/si_compute.c
View File

@ -246,6 +246,9 @@ static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe
program->ir_type = cso->ir_type;
program->input_size = cso->req_input_mem;
if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
nir_print_shader(sel->nir, stderr);
if (cso->ir_type != PIPE_SHADER_IR_NATIVE) {
if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
program->ir_type = PIPE_SHADER_IR_NIR;

10
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -55,10 +55,12 @@ static const struct debug_named_value radeonsi_debug_options[] = {
{"tcs", DBG(TCS), "Print tessellation control shaders"},
{"tes", DBG(TES), "Print tessellation evaluation shaders"},
{"cs", DBG(CS), "Print compute shaders"},
{"noir", DBG(NO_IR), "Don't print the LLVM IR"},
{"nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
{"noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
{"preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations"},
{"initnir", DBG(INIT_NIR), "Print initial input NIR when shaders are created"},
{"nir", DBG(NIR), "Print final NIR after lowering when shader variants are created"},
{"initllvm", DBG(INIT_LLVM), "Print initial LLVM IR before optimizations"},
{"llvm", DBG(LLVM), "Print final LLVM IR"},
{"asm", DBG(ASM), "Print final shaders in asm"},
/* Shader compiler options the shader cache should be aware of: */
{"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},

14
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -192,10 +192,11 @@ enum
DBG_GS = MESA_SHADER_GEOMETRY,
DBG_PS = MESA_SHADER_FRAGMENT,
DBG_CS = MESA_SHADER_COMPUTE,
DBG_NO_IR,
DBG_NO_NIR,
DBG_NO_ASM,
DBG_PREOPT_IR,
DBG_INIT_NIR,
DBG_NIR,
DBG_INIT_LLVM,
DBG_LLVM,
DBG_ASM,
/* Shader compiler options the shader cache should be aware of: */
DBG_FS_CORRECT_DERIVS_AFTER_KILL,
@ -1788,11 +1789,6 @@ static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
sctx->shader.gs.cso ? GS_ON : GS_OFF);
}
static inline bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage)
{
return sscreen->debug_flags & (1 << stage);
}
static inline bool si_get_strmout_en(struct si_context *sctx)
{
return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;

33
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -1103,6 +1103,24 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad
stages[shader->selector->stage], shader->wave_size);
}
bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage,
enum si_shader_dump_type dump_type)
{
static uint64_t filter[] = {
[SI_DUMP_SHADER_KEY] = DBG(NIR) | DBG(INIT_LLVM) | DBG(LLVM) | DBG(ASM),
[SI_DUMP_INIT_NIR] = DBG(INIT_NIR),
[SI_DUMP_NIR] = DBG(NIR),
[SI_DUMP_INIT_LLVM_IR] = DBG(INIT_LLVM),
[SI_DUMP_LLVM_IR] = DBG(LLVM),
[SI_DUMP_ASM] = DBG(ASM),
[SI_DUMP_ALWAYS] = DBG(VS) | DBG(TCS) | DBG(TES) | DBG(GS) | DBG(PS) | DBG(CS),
};
assert(dump_type < ARRAY_SIZE(filter));
return sscreen->debug_flags & (1 << stage) &&
sscreen->debug_flags & filter[dump_type];
}
static void si_shader_dump_stats(struct si_screen *sscreen, struct si_shader *shader, FILE *file,
bool check_debug_option)
{
@ -1174,10 +1192,11 @@ void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
{
gl_shader_stage stage = shader->selector->stage;
if (!check_debug_option || si_can_dump_shader(sscreen, stage))
if (!check_debug_option || si_can_dump_shader(sscreen, stage, SI_DUMP_SHADER_KEY))
si_dump_shader_key(shader, file);
if (!check_debug_option && shader->binary.llvm_ir_string) {
/* This is only used with ddebug. */
if (shader->previous_stage && shader->previous_stage->binary.llvm_ir_string) {
fprintf(file, "\n%s - previous stage - LLVM IR:\n\n", si_get_shader_name(shader));
fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
@ -1187,9 +1206,7 @@ void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
fprintf(file, "%s\n", shader->binary.llvm_ir_string);
}
if (!check_debug_option ||
(si_can_dump_shader(sscreen, stage) && !(sscreen->debug_flags & DBG(NO_ASM)))) {
if (!check_debug_option || (si_can_dump_shader(sscreen, stage, SI_DUMP_ASM))) {
fprintf(file, "\n%s:\n", si_get_shader_name(shader));
if (shader->prolog)
@ -2078,10 +2095,9 @@ si_nir_generate_gs_copy_shader(struct si_screen *sscreen,
si_nir_opts(gs_selector->screen, nir, false);
if (si_can_dump_shader(sscreen, MESA_SHADER_GEOMETRY)) {
if (si_can_dump_shader(sscreen, MESA_SHADER_GEOMETRY, SI_DUMP_NIR)) {
fprintf(stderr, "GS Copy Shader:\n");
if (!(sscreen->debug_flags & DBG(NO_NIR)))
nir_print_shader(nir, stderr);
nir_print_shader(nir, stderr);
}
bool ok = false;
@ -2167,8 +2183,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
/* Dump NIR before doing NIR->LLVM conversion in case the
* conversion fails. */
if (si_can_dump_shader(sscreen, sel->stage) &&
!(sscreen->debug_flags & DBG(NO_NIR))) {
if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_NIR)) {
nir_print_shader(nir, stderr);
if (nir->xfb_info)

12
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -325,6 +325,16 @@ enum
#define SI_PROFILE_PS_NO_BINNING (1 << 4)
#define SI_PROFILE_CLAMP_DIV_BY_ZERO (1 << 5)
enum si_shader_dump_type {
SI_DUMP_SHADER_KEY,
SI_DUMP_INIT_NIR, /* initial input NIR when shaders are created (before lowering) */
SI_DUMP_NIR, /* final NIR after lowering when shader variants are created */
SI_DUMP_INIT_LLVM_IR, /* initial LLVM IR before optimizations */
SI_DUMP_LLVM_IR, /* final LLVM IR */
SI_DUMP_ASM, /* final asm shaders */
SI_DUMP_ALWAYS,
};
/**
* For VS shader keys, describe any fixups required for vertex fetch.
*
@ -982,6 +992,8 @@ unsigned si_shader_io_get_unique_index_patch(unsigned semantic);
unsigned si_shader_io_get_unique_index(unsigned semantic, bool is_varying);
bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
uint64_t scratch_va);
bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage,
enum si_shader_dump_type dump_type);
void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
struct util_debug_callback *debug, FILE *f, bool check_debug_option);
void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shader *shader,

14
src/gallium/drivers/radeonsi/si_shader_llvm.c
View File

@ -76,14 +76,12 @@ bool si_compile_llvm(struct si_screen *sscreen, struct si_shader_binary *binary,
{
unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
if (si_can_dump_shader(sscreen, stage)) {
if (si_can_dump_shader(sscreen, stage, SI_DUMP_LLVM_IR)) {
fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
fprintf(stderr, "%s LLVM IR:\n\n", name);
ac_dump_module(ac->module);
fprintf(stderr, "\n");
}
fprintf(stderr, "%s LLVM IR:\n\n", name);
ac_dump_module(ac->module);
fprintf(stderr, "\n");
}
if (sscreen->record_llvm_ir) {
@ -255,8 +253,8 @@ void si_llvm_create_main_func(struct si_shader_context *ctx)
void si_llvm_optimize_module(struct si_shader_context *ctx)
{
/* Dump LLVM IR before any optimization passes */
if (ctx->screen->debug_flags & DBG(PREOPT_IR) && si_can_dump_shader(ctx->screen, ctx->stage))
LLVMDumpModule(ctx->ac.module);
if (si_can_dump_shader(ctx->screen, ctx->stage, SI_DUMP_INIT_LLVM_IR))
ac_dump_module(ctx->ac.module);
/* Run the pass */
LLVMRunPassManager(ctx->compiler->passmgr, ctx->ac.module);

5
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View File

@ -3066,7 +3066,7 @@ void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
struct util_async_debug_callback async_debug;
bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
si_can_dump_shader(sctx->screen, stage);
si_can_dump_shader(sctx->screen, stage, SI_DUMP_ALWAYS);
if (debug) {
u_async_debug_init(&async_debug);
@ -3154,6 +3154,9 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
sel->sampler_and_images_descriptors_index =
si_sampler_and_image_descriptors_idx(type);
if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
nir_print_shader(sel->nir, stderr);
p_atomic_inc(&sscreen->num_shaders_created);
si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
&sel->active_samplers_and_images);