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anv,radv,tu,val: Call nir_lower_io for push constants
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5275>
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@ -653,6 +653,9 @@ radv_shader_compile_to_nir(struct radv_device *device,
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*/
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nir_lower_var_copies(nir);
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
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nir_address_format_32bit_offset);
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NIR_PASS_V(nir, nir_lower_explicit_io,
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nir_var_mem_ubo | nir_var_mem_ssbo,
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nir_address_format_32bit_index_offset);
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@ -765,6 +765,9 @@ tu_shader_create(struct tu_device *dev,
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&shader->multi_pos_output, dev);
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}
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
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nir_address_format_32bit_offset);
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NIR_PASS_V(nir, nir_lower_explicit_io,
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nir_var_mem_ubo | nir_var_mem_ssbo,
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nir_address_format_vec2_index_32bit_offset);
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@ -573,6 +573,9 @@ val_shader_compile_to_ir(struct val_pipeline *pipeline,
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NIR_PASS_V(nir, nir_split_var_copies);
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NIR_PASS_V(nir, nir_lower_global_vars_to_local);
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
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nir_address_format_32bit_offset);
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if (nir->info.stage == MESA_SHADER_COMPUTE) {
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NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, shared_var_info);
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset);
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@ -765,6 +765,8 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
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nir_address_format_64bit_global);
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
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nir_address_format_32bit_offset);
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/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
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anv_nir_apply_pipeline_layout(pdevice,
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