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aco: Remove VS inputs from visit_load_input.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16805>
This commit is contained in:
Timur Kristóf
Marge Bot
parent
27c8131978
commit
c602092033
@ -313,58 +313,6 @@ as_vgpr(isel_context* ctx, Temp val)
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return as_vgpr(bld, val);
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}
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// assumes a != 0xffffffff
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void
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emit_v_div_u32(isel_context* ctx, Temp dst, Temp a, uint32_t b)
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{
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assert(b != 0);
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Builder bld(ctx->program, ctx->block);
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if (util_is_power_of_two_or_zero(b)) {
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bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand::c32(util_logbase2(b)), a);
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return;
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}
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util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
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assert(info.multiplier <= 0xffffffff);
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bool pre_shift = info.pre_shift != 0;
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bool increment = info.increment != 0;
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bool multiply = true;
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bool post_shift = info.post_shift != 0;
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if (!pre_shift && !increment && !multiply && !post_shift) {
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bld.copy(Definition(dst), a);
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return;
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}
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Temp pre_shift_dst = a;
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if (pre_shift) {
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pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
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bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand::c32(info.pre_shift),
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a);
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}
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Temp increment_dst = pre_shift_dst;
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if (increment) {
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increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
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bld.vadd32(Definition(increment_dst), Operand::c32(info.increment), pre_shift_dst);
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}
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Temp multiply_dst = increment_dst;
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if (multiply) {
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multiply_dst = post_shift ? bld.tmp(v1) : dst;
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bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
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bld.copy(bld.def(v1), Operand::c32(info.multiplier)));
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}
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if (post_shift) {
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bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand::c32(info.post_shift),
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multiply_dst);
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}
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}
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void
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emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
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{
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@ -5632,216 +5580,7 @@ visit_load_input(isel_context* ctx, nir_intrinsic_instr* instr)
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Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
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nir_src offset = *nir_get_io_offset_src(instr);
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if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
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if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
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isel_err(offset.ssa->parent_instr,
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"Unimplemented non-zero nir_intrinsic_load_input offset");
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Temp vertex_buffers =
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convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
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unsigned location = nir_intrinsic_base(instr) - VERT_ATTRIB_GENERIC0;
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unsigned bitsize = instr->dest.ssa.bit_size;
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unsigned component = nir_intrinsic_component(instr) >> (bitsize == 64 ? 1 : 0);
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unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
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uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
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uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
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enum pipe_format attrib_format =
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(enum pipe_format)ctx->options->key.vs.vertex_attribute_formats[location];
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unsigned binding_align = ctx->options->key.vs.vertex_binding_align[attrib_binding];
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const struct ac_vtx_format_info* vtx_info =
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ac_get_vtx_format_info(GFX8, CHIP_POLARIS10, attrib_format);
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unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
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unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
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unsigned desc_index =
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ctx->program->info.vs.use_per_attribute_vb_descs ? location : attrib_binding;
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desc_index = util_bitcount(ctx->program->info.vs.vb_desc_usage_mask &
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u_bit_consecutive(0, desc_index));
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Operand off = bld.copy(bld.def(s1), Operand::c32(desc_index * 16u));
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Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
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Temp index;
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if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
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uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
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Temp start_instance = get_arg(ctx, ctx->args->start_instance);
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if (divisor) {
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Temp instance_id = get_arg(ctx, ctx->args->instance_id);
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if (divisor != 1) {
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Temp divided = bld.tmp(v1);
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emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
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index = bld.vadd32(bld.def(v1), start_instance, divided);
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} else {
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index = bld.vadd32(bld.def(v1), start_instance, instance_id);
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}
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} else {
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index = bld.copy(bld.def(v1), start_instance);
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}
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} else {
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index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->base_vertex),
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get_arg(ctx, ctx->args->vertex_id));
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}
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Temp* const channels = (Temp*)alloca(num_channels * sizeof(Temp));
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unsigned channel_start = 0;
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bool direct_fetch = false;
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/* skip unused channels at the start */
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if (vtx_info->chan_byte_size) {
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channel_start = ffs(mask) - 1;
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for (unsigned i = 0; i < MIN2(channel_start, num_channels); i++)
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channels[i] = Temp(0, s1);
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}
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/* load channels */
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while (channel_start < num_channels) {
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unsigned fetch_component = num_channels - channel_start;
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unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
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/* use MUBUF when possible to avoid possible alignment issues */
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/* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
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bool use_mubuf = vtx_info->chan_byte_size == 4 && bitsize != 16;
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unsigned fetch_fmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
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if (!use_mubuf) {
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fetch_component = ac_get_safe_fetch_size(ctx->program->gfx_level, vtx_info, fetch_offset,
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vtx_info->num_channels - channel_start, binding_align,
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fetch_component);
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fetch_fmt = vtx_info->hw_format[fetch_component - 1];
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} else {
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/* GFX6 only supports loading vec3 with MTBUF, split to vec2,scalar. */
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if (fetch_component == 3 && ctx->options->gfx_level == GFX6)
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fetch_component = 2;
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}
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unsigned fetch_bytes = fetch_component * bitsize / 8;
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Temp fetch_index = index;
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if (attrib_stride != 0 && fetch_offset > attrib_stride) {
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fetch_index =
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bld.vadd32(bld.def(v1), Operand::c32(fetch_offset / attrib_stride), fetch_index);
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fetch_offset = fetch_offset % attrib_stride;
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}
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Operand soffset = Operand::zero();
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if (fetch_offset >= 4096) {
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soffset = bld.copy(bld.def(s1), Operand::c32(fetch_offset / 4096 * 4096));
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fetch_offset %= 4096;
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}
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aco_opcode opcode;
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switch (fetch_bytes) {
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case 2:
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assert(!use_mubuf && bitsize == 16);
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opcode = aco_opcode::tbuffer_load_format_d16_x;
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break;
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case 4:
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if (bitsize == 16) {
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assert(!use_mubuf);
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opcode = aco_opcode::tbuffer_load_format_d16_xy;
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} else {
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opcode =
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use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
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}
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break;
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case 6:
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assert(!use_mubuf && bitsize == 16);
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opcode = aco_opcode::tbuffer_load_format_d16_xyz;
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break;
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case 8:
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if (bitsize == 16) {
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assert(!use_mubuf);
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opcode = aco_opcode::tbuffer_load_format_d16_xyzw;
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} else {
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opcode =
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use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
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}
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break;
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case 12:
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assert(ctx->options->gfx_level >= GFX7 ||
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(!use_mubuf && ctx->options->gfx_level == GFX6));
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opcode =
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use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
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break;
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case 16:
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opcode =
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use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
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break;
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default: unreachable("Unimplemented load_input vector size");
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}
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Temp fetch_dst;
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if (channel_start == 0 && fetch_bytes == dst.bytes()) {
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direct_fetch = true;
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fetch_dst = dst;
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} else {
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fetch_dst = bld.tmp(RegClass::get(RegType::vgpr, fetch_bytes));
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}
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if (use_mubuf) {
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bld.mubuf(opcode, Definition(fetch_dst), list, fetch_index,
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soffset, fetch_offset, false, false, true);
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} else {
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unsigned dfmt = fetch_fmt & 0xf;
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unsigned nfmt = fetch_fmt >> 4;
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bld.mtbuf(opcode, Definition(fetch_dst), list, fetch_index,
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soffset, dfmt, nfmt, fetch_offset, false, true);
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}
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emit_split_vector(ctx, fetch_dst, fetch_dst.bytes() * 8 / bitsize);
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if (fetch_component == 1) {
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channels[channel_start] = fetch_dst;
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} else {
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for (unsigned i = 0; i < MIN2(fetch_component, num_channels - channel_start); i++)
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channels[channel_start + i] = emit_extract_vector(
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ctx, fetch_dst, i, RegClass::get(RegType::vgpr, bitsize / 8u));
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}
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channel_start += fetch_component;
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}
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if (!direct_fetch) {
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bool is_float =
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nir_alu_type_get_base_type(nir_intrinsic_dest_type(instr)) == nir_type_float;
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unsigned num_components = instr->dest.ssa.num_components;
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aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(
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aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
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std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
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unsigned num_temp = 0;
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for (unsigned i = 0; i < num_components; i++) {
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unsigned idx = i + component;
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if (idx < num_channels && channels[idx].id()) {
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Temp channel = channels[idx];
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vec->operands[i] = Operand(channel);
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num_temp++;
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elems[i] = channel;
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} else if (bitsize == 64) {
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/* 22.1.1. Attribute Location and Component Assignment of Vulkan 1.3 specification:
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* For 64-bit data types, no default attribute values are provided. Input variables
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* must not use more components than provided by the attribute.
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*/
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vec->operands[i] = Operand(v2);
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} else if (is_float && idx == 3) {
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vec->operands[i] = bitsize == 16 ? Operand::c16(0x3c00u) : Operand::c32(0x3f800000u);
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} else if (!is_float && idx == 3) {
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vec->operands[i] = Operand::get_const(ctx->options->gfx_level, 1u, bitsize / 8u);
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} else {
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vec->operands[i] = Operand::zero(bitsize / 8u);
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}
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}
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vec->definitions[0] = Definition(dst);
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ctx->block->instructions.emplace_back(std::move(vec));
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emit_split_vector(ctx, dst, num_components);
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if (num_temp == num_components)
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ctx->allocated_vec.emplace(dst.id(), elems);
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}
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} else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
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if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
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if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
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isel_err(offset.ssa->parent_instr,
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"Unimplemented non-zero nir_intrinsic_load_input offset");
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