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anv: Set up memory types and heaps during physical device init
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Cc: "17.1" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
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eceaf7e234
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c1f4343807
@ -97,6 +97,63 @@ anv_compute_heap_size(int fd, uint64_t *heap_size)
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return VK_SUCCESS;
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}
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static VkResult
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anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
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{
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/* The kernel query only tells us whether or not the kernel supports the
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* EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag and not whether or not the
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* hardware has actual 48bit address support.
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*/
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device->supports_48bit_addresses =
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(device->info.gen >= 8) && anv_gem_supports_48b_addresses(fd);
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uint64_t heap_size;
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VkResult result = anv_compute_heap_size(fd, &heap_size);
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if (result != VK_SUCCESS)
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return result;
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if (device->info.has_llc) {
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/* Big core GPUs share LLC with the CPU and thus one memory type can be
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* both cached and coherent at the same time.
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*/
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device->memory.type_count = 1;
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device->memory.types[0] = (VkMemoryType) {
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.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
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VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
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VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
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VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
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.heapIndex = 0,
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};
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} else {
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/* The spec requires that we expose a host-visible, coherent memory
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* type, but Atom GPUs don't share LLC. Thus we offer two memory types
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* to give the application a choice between cached, but not coherent and
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* coherent but uncached (WC though).
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*/
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device->memory.type_count = 2;
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device->memory.types[0] = (VkMemoryType) {
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.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
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VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
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VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
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.heapIndex = 0,
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};
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device->memory.types[1] = (VkMemoryType) {
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.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
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VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
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VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
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.heapIndex = 0,
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};
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}
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device->memory.heap_count = 1;
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device->memory.heaps[0] = (VkMemoryHeap) {
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.size = heap_size,
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.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
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};
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return VK_SUCCESS;
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}
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static VkResult
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anv_physical_device_init_uuids(struct anv_physical_device *device)
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{
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@ -225,14 +282,7 @@ anv_physical_device_init(struct anv_physical_device *device,
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goto fail;
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}
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/* The kernel query only tells us whether or not the kernel supports the
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* EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag and not whether or not the
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* hardware has actual 48bit address support.
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*/
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device->supports_48bit_addresses =
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(device->info.gen >= 8) && anv_gem_supports_48b_addresses(fd);
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result = anv_compute_heap_size(fd, &device->heap_size);
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result = anv_physical_device_init_heaps(device, fd);
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if (result != VK_SUCCESS)
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goto fail;
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@ -885,44 +935,21 @@ void anv_GetPhysicalDeviceMemoryProperties(
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{
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ANV_FROM_HANDLE(anv_physical_device, physical_device, physicalDevice);
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if (physical_device->info.has_llc) {
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/* Big core GPUs share LLC with the CPU and thus one memory type can be
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* both cached and coherent at the same time.
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*/
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pMemoryProperties->memoryTypeCount = 1;
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pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
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.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
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VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
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VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
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VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
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.heapIndex = 0,
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};
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} else {
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/* The spec requires that we expose a host-visible, coherent memory
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* type, but Atom GPUs don't share LLC. Thus we offer two memory types
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* to give the application a choice between cached, but not coherent and
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* coherent but uncached (WC though).
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*/
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pMemoryProperties->memoryTypeCount = 2;
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pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
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.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
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VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
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VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
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.heapIndex = 0,
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};
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pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
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.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
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VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
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VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
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.heapIndex = 0,
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pMemoryProperties->memoryTypeCount = physical_device->memory.type_count;
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for (uint32_t i = 0; i < physical_device->memory.type_count; i++) {
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pMemoryProperties->memoryTypes[i] = (VkMemoryType) {
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.propertyFlags = physical_device->memory.types[i].propertyFlags,
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.heapIndex = physical_device->memory.types[i].heapIndex,
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};
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}
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pMemoryProperties->memoryHeapCount = 1;
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pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
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.size = physical_device->heap_size,
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.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
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};
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pMemoryProperties->memoryHeapCount = physical_device->memory.heap_count;
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for (uint32_t i = 0; i < physical_device->memory.heap_count; i++) {
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pMemoryProperties->memoryHeaps[i] = (VkMemoryHeap) {
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.size = physical_device->memory.heaps[i].size,
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.flags = physical_device->memory.heaps[i].flags,
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};
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}
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}
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void anv_GetPhysicalDeviceMemoryProperties2KHR(
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@ -656,7 +656,6 @@ struct anv_physical_device {
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* practically unlimited. However, we will never report more than 3/4 of
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* the total system ram to try and avoid running out of RAM.
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*/
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uint64_t heap_size;
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bool supports_48bit_addresses;
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struct brw_compiler * compiler;
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struct isl_device isl_dev;
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@ -666,6 +665,13 @@ struct anv_physical_device {
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uint32_t eu_total;
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uint32_t subslice_total;
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struct {
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uint32_t type_count;
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VkMemoryType types[VK_MAX_MEMORY_TYPES];
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uint32_t heap_count;
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VkMemoryHeap heaps[VK_MAX_MEMORY_HEAPS];
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} memory;
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uint8_t pipeline_cache_uuid[VK_UUID_SIZE];
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uint8_t driver_uuid[VK_UUID_SIZE];
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uint8_t device_uuid[VK_UUID_SIZE];
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