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radv: Set SCRATCH_EN for RT pipelines based on dynamic stack size

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Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27899>
(cherry picked from commit 4c05ebf3a5)
This commit is contained in:
Friedrich Vock 2024-03-02 17:46:33 +01:00 committed by Eric Engestrom
parent c154218160
commit b89310ffed
3 changed files with 17 additions and 4 deletions
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2
.pick_status.json
View File

@ -1084,7 +1084,7 @@
"description": "radv: Set SCRATCH_EN for RT pipelines based on dynamic stack size",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

15
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -9846,6 +9846,17 @@ radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPip
radv_flush_constants(cmd_buffer, pc_stages, bind_point);
}
static void
radv_emit_rt_stack_size(struct radv_cmd_buffer *cmd_buffer)
{
unsigned rsrc2 = cmd_buffer->state.rt_prolog->config.rsrc2;
if (cmd_buffer->state.rt_stack_size)
rsrc2 |= S_00B12C_SCRATCH_EN(1);
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 3);
radeon_set_sh_reg(cmd_buffer->cs, R_00B84C_COMPUTE_PGM_RSRC2, rsrc2);
}
static void
radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info,
struct radv_compute_pipeline *pipeline, struct radv_shader *compute_shader,
@ -9867,6 +9878,8 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
* packets between the wait and the draw)
*/
radv_emit_compute_pipeline(cmd_buffer, pipeline);
if (bind_point == VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR)
radv_emit_rt_stack_size(cmd_buffer);
radv_emit_cache_flush(cmd_buffer);
/* <-- CUs are idle here --> */
@ -9895,6 +9908,8 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_inf
radv_upload_compute_shader_descriptors(cmd_buffer, bind_point);
radv_emit_compute_pipeline(cmd_buffer, pipeline);
if (bind_point == VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR)
radv_emit_rt_stack_size(cmd_buffer);
radv_emit_dispatch_packets(cmd_buffer, compute_shader, info);
}

4
src/amd/vulkan/radv_shader.c
View File

@ -1571,7 +1571,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
const struct radv_shader_info *info = &binary->info;
gl_shader_stage stage = binary->info.stage;
const struct radv_physical_device *pdevice = device->physical_device;
bool scratch_enabled = config->scratch_bytes_per_wave > 0 || info->cs.is_rt_shader;
bool scratch_enabled = config->scratch_bytes_per_wave > 0;
bool trap_enabled = !!device->trap_handler_shader;
unsigned vgpr_comp_cnt = 0;
unsigned num_input_vgprs = args->ac.num_vgprs_used;
@ -1717,8 +1717,6 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
case MESA_SHADER_CALLABLE:
case MESA_SHADER_INTERSECTION:
case MESA_SHADER_ANY_HIT:
config->rsrc2 |= S_00B12C_SCRATCH_EN(1);
FALLTHROUGH;
case MESA_SHADER_COMPUTE:
case MESA_SHADER_TASK:
config->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.gfx_level >= GFX10) | S_00B848_WGP_MODE(wgp_mode);