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gallium: use "ull" number suffix to keep the QtCreator parser happy

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It can't parse "llu".

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
This commit is contained in:
Marek Olšák 2017-07-06 02:23:46 +02:00
parent 833108ac14
commit aaee0d1bbf
11 changed files with 39 additions and 39 deletions
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2
include/GL/internal/dri_interface.h
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@ -342,7 +342,7 @@ struct __DRI2throttleExtensionRec {
#define __DRI2_FENCE "DRI2_Fence" #define __DRI2_FENCE "DRI2_Fence"
#define __DRI2_FENCE_VERSION 2 #define __DRI2_FENCE_VERSION 2
#define __DRI2_FENCE_TIMEOUT_INFINITE 0xffffffffffffffffllu #define __DRI2_FENCE_TIMEOUT_INFINITE 0xffffffffffffffffull
#define __DRI2_FENCE_FLAG_FLUSH_COMMANDS (1 << 0) #define __DRI2_FENCE_FLAG_FLUSH_COMMANDS (1 << 0)

4
src/gallium/drivers/r600/r600_state_common.c
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@ -847,11 +847,11 @@ static void *r600_create_shader_state(struct pipe_context *ctx,
case TGSI_SEMANTIC_TESSOUTER: case TGSI_SEMANTIC_TESSOUTER:
case TGSI_SEMANTIC_PATCH: case TGSI_SEMANTIC_PATCH:
sel->lds_patch_outputs_written_mask |= sel->lds_patch_outputs_written_mask |=
1llu << r600_get_lds_unique_index(name, index); 1ull << r600_get_lds_unique_index(name, index);
break; break;
default: default:
sel->lds_outputs_written_mask |= sel->lds_outputs_written_mask |=
1llu << r600_get_lds_unique_index(name, index); 1ull << r600_get_lds_unique_index(name, index);
} }
} }
break; break;

44
src/gallium/drivers/radeon/r600_pipe_common.h
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@ -90,28 +90,28 @@
#define DBG_TEST_DMA (1 << 20) #define DBG_TEST_DMA (1 << 20)
/* Bits 21-31 are reserved for the r600g driver. */ /* Bits 21-31 are reserved for the r600g driver. */
/* features */ /* features */
#define DBG_NO_ASYNC_DMA (1llu << 32) #define DBG_NO_ASYNC_DMA (1ull << 32)
#define DBG_NO_HYPERZ (1llu << 33) #define DBG_NO_HYPERZ (1ull << 33)
#define DBG_NO_DISCARD_RANGE (1llu << 34) #define DBG_NO_DISCARD_RANGE (1ull << 34)
#define DBG_NO_2D_TILING (1llu << 35) #define DBG_NO_2D_TILING (1ull << 35)
#define DBG_NO_TILING (1llu << 36) #define DBG_NO_TILING (1ull << 36)
#define DBG_SWITCH_ON_EOP (1llu << 37) #define DBG_SWITCH_ON_EOP (1ull << 37)
#define DBG_FORCE_DMA (1llu << 38) #define DBG_FORCE_DMA (1ull << 38)
#define DBG_PRECOMPILE (1llu << 39) #define DBG_PRECOMPILE (1ull << 39)
#define DBG_INFO (1llu << 40) #define DBG_INFO (1ull << 40)
#define DBG_NO_WC (1llu << 41) #define DBG_NO_WC (1ull << 41)
#define DBG_CHECK_VM (1llu << 42) #define DBG_CHECK_VM (1ull << 42)
#define DBG_NO_DCC (1llu << 43) #define DBG_NO_DCC (1ull << 43)
#define DBG_NO_DCC_CLEAR (1llu << 44) #define DBG_NO_DCC_CLEAR (1ull << 44)
#define DBG_NO_RB_PLUS (1llu << 45) #define DBG_NO_RB_PLUS (1ull << 45)
#define DBG_SI_SCHED (1llu << 46) #define DBG_SI_SCHED (1ull << 46)
#define DBG_MONOLITHIC_SHADERS (1llu << 47) #define DBG_MONOLITHIC_SHADERS (1ull << 47)
#define DBG_NO_CE (1llu << 48) #define DBG_NO_CE (1ull << 48)
#define DBG_UNSAFE_MATH (1llu << 49) #define DBG_UNSAFE_MATH (1ull << 49)
#define DBG_NO_DCC_FB (1llu << 50) #define DBG_NO_DCC_FB (1ull << 50)
#define DBG_TEST_VMFAULT_CP (1llu << 51) #define DBG_TEST_VMFAULT_CP (1ull << 51)
#define DBG_TEST_VMFAULT_SDMA (1llu << 52) #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
#define DBG_TEST_VMFAULT_SHADER (1llu << 53) #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
#define R600_MAP_BUFFER_ALIGNMENT 64 #define R600_MAP_BUFFER_ALIGNMENT 64
#define R600_MAX_VIEWPORTS 16 #define R600_MAX_VIEWPORTS 16

2
src/gallium/drivers/radeonsi/si_cp_dma.c
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@ -215,7 +215,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
if (!size) if (!size)
return; return;
dma_clear_size = size & ~3llu; dma_clear_size = size & ~3ull;
/* Mark the buffer range of destination as valid (initialized), /* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping * so that transfer_map knows it should wait for the GPU when mapping

4
src/gallium/drivers/radeonsi/si_debug.c
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@ -344,7 +344,7 @@ static void si_dump_bo_list(struct si_context *sctx,
/* Print the usage. */ /* Print the usage. */
for (j = 0; j < 64; j++) { for (j = 0; j < 64; j++) {
if (!(saved->bo_list[i].priority_usage & (1llu << j))) if (!(saved->bo_list[i].priority_usage & (1ull << j)))
continue; continue;
fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j)); fprintf(f, "%s%s", !hit ? "" : ", ", priority_to_string(j));
@ -894,7 +894,7 @@ static bool si_vm_fault_occured(struct si_context *sctx, uint32_t *out_addr)
} }
continue; continue;
} }
timestamp = sec * 1000000llu + usec; timestamp = sec * 1000000ull + usec;
/* If just updating the timestamp. */ /* If just updating the timestamp. */
if (!out_addr) if (!out_addr)

2
src/gallium/drivers/radeonsi/si_shader.c
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@ -7138,7 +7138,7 @@ static void si_build_ps_epilog_function(struct si_shader_context *ctx,
if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) { if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
/* Just set this if any of the colorbuffers are enabled. */ /* Just set this if any of the colorbuffers are enabled. */
if (spi_format & if (spi_format &
((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1)) ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
last_color_export = 0; last_color_export = 0;
} else { } else {
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)

10
src/gallium/drivers/radeonsi/si_state_shaders.c
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@ -2035,8 +2035,8 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
case PIPE_SHADER_TESS_CTRL: case PIPE_SHADER_TESS_CTRL:
/* Always reserve space for these. */ /* Always reserve space for these. */
sel->patch_outputs_written |= sel->patch_outputs_written |=
(1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) | (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
(1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0)); (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
/* fall through */ /* fall through */
case PIPE_SHADER_VERTEX: case PIPE_SHADER_VERTEX:
case PIPE_SHADER_TESS_EVAL: case PIPE_SHADER_TESS_EVAL:
@ -2049,7 +2049,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
case TGSI_SEMANTIC_TESSOUTER: case TGSI_SEMANTIC_TESSOUTER:
case TGSI_SEMANTIC_PATCH: case TGSI_SEMANTIC_PATCH:
sel->patch_outputs_written |= sel->patch_outputs_written |=
1llu << si_shader_io_get_unique_index_patch(name, index); 1ull << si_shader_io_get_unique_index_patch(name, index);
break; break;
case TGSI_SEMANTIC_GENERIC: case TGSI_SEMANTIC_GENERIC:
@ -2059,7 +2059,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
/* fall through */ /* fall through */
default: default:
sel->outputs_written |= sel->outputs_written |=
1llu << si_shader_io_get_unique_index(name, index); 1ull << si_shader_io_get_unique_index(name, index);
break; break;
case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */ case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
case TGSI_SEMANTIC_EDGEFLAG: case TGSI_SEMANTIC_EDGEFLAG:
@ -2088,7 +2088,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
/* fall through */ /* fall through */
default: default:
sel->inputs_read |= sel->inputs_read |=
1llu << si_shader_io_get_unique_index(name, index); 1ull << si_shader_io_get_unique_index(name, index);
break; break;
case TGSI_SEMANTIC_PCOORD: /* ignore this */ case TGSI_SEMANTIC_PCOORD: /* ignore this */
break; break;

2
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
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@ -536,7 +536,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
buffer = &cs->sparse_buffers[index]; buffer = &cs->sparse_buffers[index];
} }
buffer->u.real.priority_usage |= 1llu << priority; buffer->u.real.priority_usage |= 1ull << priority;
buffer->usage |= usage; buffer->usage |= usage;
cs->last_added_bo = bo; cs->last_added_bo = bo;

2
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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@ -367,7 +367,7 @@ static unsigned radeon_drm_cs_add_buffer(struct radeon_winsys_cs *rcs,
reloc->read_domains |= rd; reloc->read_domains |= rd;
reloc->write_domain |= wd; reloc->write_domain |= wd;
reloc->flags = MAX2(reloc->flags, priority); reloc->flags = MAX2(reloc->flags, priority);
cs->csc->relocs_bo[index].u.real.priority_usage |= 1llu << priority; cs->csc->relocs_bo[index].u.real.priority_usage |= 1ull << priority;
if (added_domains & RADEON_DOMAIN_VRAM) if (added_domains & RADEON_DOMAIN_VRAM)
cs->base.used_vram += bo->base.size; cs->base.used_vram += bo->base.size;

4
src/mesa/state_tracker/st_atom.h
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@ -68,7 +68,7 @@ enum {
/* Define ST_NEW_xxx values as static const uint64_t values. /* Define ST_NEW_xxx values as static const uint64_t values.
* We can't use an enum type because MSVC doesn't allow 64-bit enum values. * We can't use an enum type because MSVC doesn't allow 64-bit enum values.
*/ */
#define ST_STATE(FLAG, st_update) static const uint64_t FLAG = 1llu << FLAG##_INDEX; #define ST_STATE(FLAG, st_update) static const uint64_t FLAG = 1ull << FLAG##_INDEX;
#include "st_atom_list.h" #include "st_atom_list.h"
#undef ST_STATE #undef ST_STATE
@ -145,7 +145,7 @@ enum {
/* All state flags within each group: */ /* All state flags within each group: */
#define ST_PIPELINE_RENDER_STATE_MASK (ST_NEW_CS_STATE - 1) #define ST_PIPELINE_RENDER_STATE_MASK (ST_NEW_CS_STATE - 1)
#define ST_PIPELINE_COMPUTE_STATE_MASK (0xffllu << ST_NEW_CS_STATE_INDEX) #define ST_PIPELINE_COMPUTE_STATE_MASK (0xffull << ST_NEW_CS_STATE_INDEX)
#define ST_PIPELINE_CLEAR_STATE_MASK (ST_NEW_FB_STATE | \ #define ST_PIPELINE_CLEAR_STATE_MASK (ST_NEW_FB_STATE | \
ST_NEW_SCISSOR | \ ST_NEW_SCISSOR | \
ST_NEW_WINDOW_RECTANGLES) ST_NEW_WINDOW_RECTANGLES)

2
src/util/bitscan.h
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@ -136,7 +136,7 @@ u_bit_scan_consecutive_range(unsigned *mask, int *start, int *count)
static inline void static inline void
u_bit_scan_consecutive_range64(uint64_t *mask, int *start, int *count) u_bit_scan_consecutive_range64(uint64_t *mask, int *start, int *count)
{ {
if (*mask == ~0llu) { if (*mask == ~0ull) {
*start = 0; *start = 0;
*count = 64; *count = 64;
*mask = 0; *mask = 0;