freedreno/fdl: Pass fd_dev_info to fdl6_layout

In the next commit we will need to make a decision about layouts
based on GPU capabilities.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31631>
This commit is contained in:
Danylo Piliaiev 2024-11-12 13:30:53 +01:00 committed by Marge Bot
parent 4ccbc924b5
commit 9fc01ec4df
10 changed files with 35 additions and 20 deletions

View File

@ -88,8 +88,11 @@ main(int argc, char **argv)
{
int ret = 0;
struct fd_dev_id a540_dev_id = {
.gpu_id = 540,
};
for (int i = 0; i < ARRAY_SIZE(testcases); i++) {
if (!fdl_test_layout(&testcases[i], 540))
if (!fdl_test_layout(&testcases[i], &a540_dev_id))
ret = 1;
}

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@ -101,10 +101,11 @@ fdl6_tile_alignment(struct fdl_layout *layout, uint32_t *heightalign)
* piglit/bin/texelFetch fs sampler3D 100x100x8
*/
bool
fdl6_layout(struct fdl_layout *layout, enum pipe_format format,
uint32_t nr_samples, uint32_t width0, uint32_t height0,
uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
bool is_3d, struct fdl_explicit_layout *explicit_layout)
fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
enum pipe_format format, uint32_t nr_samples, uint32_t width0,
uint32_t height0, uint32_t depth0, uint32_t mip_levels,
uint32_t array_size, bool is_3d,
struct fdl_explicit_layout *explicit_layout)
{
uint32_t offset = 0, heightalign;
uint32_t ubwc_blockwidth, ubwc_blockheight;

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@ -968,8 +968,11 @@ main(int argc, char **argv)
{
int ret = 0;
struct fd_dev_id a630_dev_id = {
.gpu_id = 630,
};
for (int i = 0; i < ARRAY_SIZE(testcases); i++) {
if (!fdl_test_layout(&testcases[i], 630))
if (!fdl_test_layout(&testcases[i], &a630_dev_id))
ret = 1;
}

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@ -12,7 +12,7 @@
#include <stdio.h>
bool
fdl_test_layout(const struct testcase *testcase, int gpu_id)
fdl_test_layout(const struct testcase *testcase, const struct fd_dev_id *dev_id)
{
struct fdl_layout layout = {
.ubwc = testcase->layout.ubwc,
@ -28,14 +28,15 @@ fdl_test_layout(const struct testcase *testcase, int gpu_id)
max_size = u_minify(max_size, 1);
}
if (gpu_id >= 600) {
fdl6_layout(&layout, testcase->format,
if (fd_dev_gen(dev_id) >= 6) {
const struct fd_dev_info *dev_info = fd_dev_info_raw(dev_id);
fdl6_layout(&layout, dev_info, testcase->format,
MAX2(testcase->layout.nr_samples, 1), testcase->layout.width0,
MAX2(testcase->layout.height0, 1),
MAX2(testcase->layout.depth0, 1), mip_levels,
MAX2(testcase->array_size, 1), testcase->is_3d, NULL);
} else {
assert(gpu_id >= 500);
assert(fd_dev_gen(dev_id) >= 5);
fdl5_layout(&layout, testcase->format,
MAX2(testcase->layout.nr_samples, 1), testcase->layout.width0,
MAX2(testcase->layout.height0, 1),

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@ -3,6 +3,8 @@
* SPDX-License-Identifier: MIT
*/
#include "common/freedreno_dev_info.h"
struct testcase {
enum pipe_format format;
@ -28,4 +30,4 @@ struct testcase {
} layout;
};
bool fdl_test_layout(const struct testcase *testcase, int gpu_id);
bool fdl_test_layout(const struct testcase *testcase, const struct fd_dev_id *dev_id);

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@ -14,6 +14,7 @@
#include "util/u_math.h"
#include "common/freedreno_common.h"
#include "common/freedreno_dev_info.h"
BEGINC;
@ -235,10 +236,11 @@ void fdl5_layout(struct fdl_layout *layout, enum pipe_format format,
uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
bool is_3d);
bool fdl6_layout(struct fdl_layout *layout, enum pipe_format format,
uint32_t nr_samples, uint32_t width0, uint32_t height0,
uint32_t depth0, uint32_t mip_levels, uint32_t array_size,
bool is_3d, struct fdl_explicit_layout *plane_layout);
bool fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
enum pipe_format format, uint32_t nr_samples, uint32_t width0,
uint32_t height0, uint32_t depth0, uint32_t mip_levels,
uint32_t array_size, bool is_3d,
struct fdl_explicit_layout *plane_layout);
static inline void
fdl_set_pitchalign(struct fdl_layout *layout, unsigned pitchalign)

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@ -15,7 +15,7 @@ libfreedreno_layout = static_library(
include_directories : [inc_freedreno, inc_include, inc_src],
c_args : [no_override_init_args],
gnu_symbol_visibility : 'hidden',
dependencies : [idep_nir_headers, idep_mesautil],
dependencies : [idep_nir_headers, idep_mesautil, idep_libfreedreno_common],
build_by_default : false,
)
@ -30,7 +30,7 @@ foreach major : ['5', '6']
freedreno_xml_header_files,
],
link_with: libfreedreno_layout,
dependencies : idep_mesautil,
dependencies : [idep_mesautil, idep_libfreedreno_common],
include_directories: [
inc_include,
inc_src,

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@ -2903,6 +2903,7 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd,
vk_image_subresource_layer_count(&src_image->vk,
&info->srcSubresource);
fdl6_layout(&staging_layout,
&cmd->device->physical_device->dev_info,
src_format,
src_image->layout[0].nr_samples,
extent.width,

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@ -542,7 +542,7 @@ tu_image_update_layout(struct tu_device *device, struct tu_image *image,
layout->tile_mode = tile_mode;
layout->ubwc = image->ubwc_enabled;
if (!fdl6_layout(layout, format,
if (!fdl6_layout(layout, &device->physical_device->dev_info, format,
image->vk.samples,
width0, height0,
image->vk.extent.depth,

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@ -285,6 +285,7 @@ static uint32_t
fd6_setup_slices(struct fd_resource *rsc)
{
struct pipe_resource *prsc = &rsc->b.b;
struct fd_screen *screen = fd_screen(prsc->screen);
if (!FD_DBG(NOLRZ) && has_depth(prsc->format) && !is_z32(prsc->format))
setup_lrz<CHIP>(rsc);
@ -292,7 +293,7 @@ fd6_setup_slices(struct fd_resource *rsc)
if (rsc->layout.ubwc && !ok_ubwc_format(prsc->screen, prsc->format, prsc->nr_samples))
rsc->layout.ubwc = false;
fdl6_layout(&rsc->layout, prsc->format, fd_resource_nr_samples(prsc),
fdl6_layout(&rsc->layout, screen->info, prsc->format, fd_resource_nr_samples(prsc),
prsc->width0, prsc->height0, prsc->depth0, prsc->last_level + 1,
prsc->array_size, prsc->target == PIPE_TEXTURE_3D, NULL);
@ -303,6 +304,7 @@ static int
fill_ubwc_buffer_sizes(struct fd_resource *rsc)
{
struct pipe_resource *prsc = &rsc->b.b;
struct fd_screen *screen = fd_screen(prsc->screen);
struct fdl_explicit_layout l = {
.offset = rsc->layout.slices[0].offset,
.pitch = rsc->layout.pitch0,
@ -314,7 +316,7 @@ fill_ubwc_buffer_sizes(struct fd_resource *rsc)
rsc->layout.ubwc = true;
rsc->layout.tile_mode = TILE6_3;
if (!fdl6_layout(&rsc->layout, prsc->format, fd_resource_nr_samples(prsc),
if (!fdl6_layout(&rsc->layout, screen->info, prsc->format, fd_resource_nr_samples(prsc),
prsc->width0, prsc->height0, prsc->depth0,
prsc->last_level + 1, prsc->array_size, false, &l))
return -1;