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amd: add support for Arcturus
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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commit
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@ -254,6 +254,10 @@ CHIPSET(0x66AF, VEGA20)
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CHIPSET(0x15DD, RAVEN)
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CHIPSET(0x15D8, RAVEN)
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CHIPSET(0x738C, ARCTURUS)
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CHIPSET(0x7388, ARCTURUS)
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CHIPSET(0x738E, ARCTURUS)
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CHIPSET(0x7310, NAVI10)
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CHIPSET(0x7312, NAVI10)
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CHIPSET(0x7318, NAVI10)
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@ -94,6 +94,8 @@
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#define AMDGPU_RAVEN_RANGE 0x01, 0x81
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#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
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#define AMDGPU_ARCTURUS_RANGE 0x32, 0xFF
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#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
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#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
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#define AMDGPU_NAVI14_RANGE 0x14, 0x28
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@ -140,6 +142,8 @@
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#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
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#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
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#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
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#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
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#define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12)
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#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
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@ -133,6 +133,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
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return "gfx906";
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case CHIP_RAVEN2:
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return HAVE_LLVM >= 0x0800 ? "gfx909" : "gfx902";
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case CHIP_ARCTURUS:
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return "gfx908";
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case CHIP_NAVI10:
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return "gfx1010";
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case CHIP_NAVI12:
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@ -97,6 +97,7 @@ enum radeon_family {
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CHIP_VEGA20,
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CHIP_RAVEN,
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CHIP_RAVEN2,
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CHIP_ARCTURUS,
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CHIP_NAVI10,
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CHIP_NAVI12,
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CHIP_NAVI14,
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