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isl: Refactor WA 22015614752

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Using intel_needs_workaround() within a block of GFX version
checker requires extra carefulness on the road because both
of them specify a range of applicable platforms. The WA block
can be unexpectedly skipped once the GFX version checker gets
updated later.

Moving the WA implementation out of the GFX block to decouple
them for more clarity and less chance of messing up next time.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31496>
This commit is contained in:
Jianxun Zhang 2024-10-01 14:48:09 -07:00 committed by Marge Bot
parent 4d23156127
commit 705555b6b0
1 changed files with 18 additions and 46 deletions
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64
src/intel/isl/isl.c
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@ -3135,6 +3135,24 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (isl_tiling_is_std_y(surf->tiling))
return false;
/* Wa_22015614752: There are issues with multiple engines accessing
* the same CCS cacheline in parallel. This can happen if this image
* has multiple subresources. Such conflicts can be avoided with
* tilings that set the subresource alignment to 64K and with miptails
* disabled. If we aren't using such a configuration, disable CCS.
*/
if (intel_needs_workaround(dev->info, 22015614752) &&
(surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
(surf->levels > 1 ||
surf->logical_level0_px.depth > 1 ||
surf->logical_level0_px.array_len > 1)) {
assert(surf->miptail_start_level >= surf->levels);
if (surf->tiling != ISL_TILING_64) {
assert(surf->tiling == ISL_TILING_4);
return false;
}
}
if (ISL_GFX_VER(dev) >= 12) {
if (isl_surf_usage_is_stencil(surf->usage)) {
/* HiZ and MCS aren't allowed with stencil */
@ -3143,21 +3161,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
/* Multi-sampled stencil cannot have CCS */
if (surf->samples > 1)
return false;
/* Wa_22015614752: There are issues with multiple engines accessing
* the same CCS cacheline in parallel. We need a 64KB alignment
* between image subresources in order to avoid those issues, but as
* can be seen from isl_gfx125_filter_tiling, we can't use Tile64 to
* achieve that for 3D surfaces. We're limited to rely on other
* layout parameters which can't help us to achieve the target
* in all cases. So, we choose to disable CCS.
*/
if (intel_needs_workaround(dev->info, 22015614752) &&
(surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
surf->dim == ISL_SURF_DIM_3D) {
assert(surf->tiling == ISL_TILING_4);
return false;
}
} else if (isl_surf_usage_is_depth(surf->usage)) {
const struct isl_surf *hiz_surf = hiz_or_mcs_surf;
@ -3165,21 +3168,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (hiz_surf == NULL || hiz_surf->size_B == 0)
return false;
/* Wa_22015614752: There are issues with multiple engines accessing
* the same CCS cacheline in parallel. We need a 64KB alignment
* between image subresources in order to avoid those issues, but as
* can be seen from isl_gfx125_filter_tiling, we can't use Tile64 to
* achieve that for 3D surfaces. We're limited to rely on other
* layout parameters which can't help us to achieve the target
* in all cases. So, we choose to disable CCS.
*/
if (intel_needs_workaround(dev->info, 22015614752) &&
(surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
surf->dim == ISL_SURF_DIM_3D) {
assert(surf->tiling == ISL_TILING_4);
return false;
}
assert(hiz_surf->usage & ISL_SURF_USAGE_HIZ_BIT);
assert(hiz_surf->tiling == ISL_TILING_HIZ);
assert(isl_format_is_hiz(hiz_surf->format));
@ -3218,22 +3206,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
}
}
if (intel_needs_workaround(dev->info, 22015614752) &&
(surf->usage & ISL_SURF_USAGE_MULTI_ENGINE_PAR_BIT) &&
(surf->levels > 1 ||
surf->logical_level0_px.depth > 1 ||
surf->logical_level0_px.array_len > 1)) {
/* There are issues with multiple engines accessing the same CCS
* cacheline in parallel. This can happen if this image has multiple
* subresources. Such conflicts can be avoided with tilings that set
* the subresource alignment to 64K and with miptails disabled. If we
* aren't using such a configuration, disable CCS.
*/
assert(surf->miptail_start_level >= surf->levels);
if (surf->tiling != ISL_TILING_64)
return false;
}
/* BSpec 44930: (Gfx12, Gfx12.5)
*
* "Compression of 3D Ys surfaces with 64 or 128 bpp is not supported