freedreno/ir3: Don't force RTNE if rounding mode is undefined

Forcing round-to-nearest-even results in loss of opportunities for
conversion folding, causing a regression in gfxbench gl_alu2.

Fixes: de195671bd ("ir3: nir_op_f2f16 should round to even")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10773>
(cherry picked from commit 6c530ebf40)
This commit is contained in:
Rob Clark 2021-05-12 10:15:03 -07:00 committed by Eric Engestrom
parent fd630afd32
commit 6f7aa6f8c8
3 changed files with 49 additions and 42 deletions

View File

@ -27778,7 +27778,7 @@
"description": "freedreno/ir3: Don't force RTNE if rounding mode is undefined",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "de195671bdb4fde7cdebd6cecd28206d08551d15"
},

View File

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# a530/a630: grid-like rendering glitches since "ir3: nir_op_f2f16 should round to even"
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@ -104,9 +104,9 @@ traces:
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@ -120,17 +120,17 @@ traces:
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@ -158,7 +158,7 @@ traces:
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@ -166,23 +166,23 @@ traces:
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@ -220,15 +220,15 @@ traces:
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@ -236,17 +236,17 @@ traces:
# Some speckling on the main specular highlight on a530/a630 that may just be
# mediump artifacts
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@ -262,42 +262,42 @@ traces:
# Some speckling on the main specular highlight on a530/a630 that may just be
# mediump artifacts
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# Crashes on a3xx?
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# checksum: 1ae1036fcaae693b3bf36a1d2d6bbc64
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expectations:
# inner rings are flat shaded when they should be smooth

View File

@ -259,8 +259,15 @@ create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
struct ir3_instruction *cov =
ir3_COV(ctx->block, src, src_type, dst_type);
if (op == nir_op_f2f16 || op == nir_op_f2f16_rtne)
if (op == nir_op_f2f16_rtne) {
cov->regs[0]->flags |= IR3_REG_EVEN;
} else if (op == nir_op_f2f16) {
unsigned execution_mode = ctx->s->info.float_controls_execution_mode;
nir_rounding_mode rounding_mode =
nir_get_rounding_mode_from_float_controls(execution_mode, nir_type_float16);
if (rounding_mode == nir_rounding_mode_rtne)
cov->regs[0]->flags |= IR3_REG_EVEN;
}
return cov;
}