v3d: add load_fep_w_v3d intrinsic

This intrinsic helps to read the W coordinate stored in the QPU register
when initializing the input data for the fragment shaders.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28072>
This commit is contained in:
Juan A. Suarez Romero 2024-03-07 17:50:56 +01:00 committed by Marge Bot
parent 4e720f1fef
commit 62e1dff256
4 changed files with 9 additions and 0 deletions

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@ -3543,6 +3543,10 @@ ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
vir_emit_tlb_color_read(c, instr);
break;
case nir_intrinsic_load_fep_w_v3d:
ntq_store_def(c, &instr->def, 0, vir_MOV(c, c->payload_w));
break;
case nir_intrinsic_load_input:
ntq_emit_load_input(c, instr);
break;

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@ -156,6 +156,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr,
case nir_intrinsic_load_xfb_address:
case nir_intrinsic_load_num_vertices:
case nir_intrinsic_load_fb_layers_v3d:
case nir_intrinsic_load_fep_w_v3d:
case nir_intrinsic_load_tcs_num_patches_amd:
case nir_intrinsic_load_patch_vertices_in:
case nir_intrinsic_load_ring_tess_factors_amd:

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@ -1750,6 +1750,9 @@ store("tlb_sample_color_v3d", [1], [BASE, COMPONENT, SRC_TYPE], [])
# the target framebuffer
intrinsic("load_fb_layers_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER])
# V3D-specific intrinsic to load W coordinate from the fragment shader payload
intrinsic("load_fep_w_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER])
# Active invocation index within the subgroup.
# Equivalent to popcount(ballot(true) & ((1 << subgroup_invocation) - 1))
system_value("active_subgroup_invocation_agx", 1)

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@ -172,6 +172,7 @@ can_move_intrinsic(nir_intrinsic_instr *instr, opt_preamble_ctx *ctx)
case nir_intrinsic_load_line_width:
case nir_intrinsic_load_aa_line_width:
case nir_intrinsic_load_fb_layers_v3d:
case nir_intrinsic_load_fep_w_v3d:
case nir_intrinsic_load_tcs_num_patches_amd:
case nir_intrinsic_load_sample_positions_pan:
case nir_intrinsic_load_pipeline_stat_query_enabled_amd: