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freedreno: Update HLSQ_*_CMD registers for a7xx

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These are used when reading CP_MEMPOOL contents in devcoredumps and in
SQE source.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27266>
This commit is contained in:
Connor Abbott 2024-01-25 06:53:08 -05:00 committed by Marge Bot
parent 13fdde0c7d
commit 59192b851f
1 changed files with 16 additions and 3 deletions
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19
src/freedreno/registers/adreno/a6xx.xml
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@ -6129,15 +6129,15 @@ to upconvert to 32b float internally?
<bitfield name="UNK6" pos="6" type="boolean"/>
</reg32>
<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD" variants="A6XX">
<bitfield name="STATE_ID" low="0" high="7"/>
</reg32>
<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD" variants="A6XX">
<bitfield name="STATE_ID" low="0" high="7"/>
</reg32>
<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD" variants="A6XX">
<!-- I think only the low bit is actually used? -->
<bitfield name="STATE_ID" low="16" high="23"/>
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
@ -6170,6 +6170,19 @@ to upconvert to 32b float internally?
<bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
</reg32>
<reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-">
<bitfield name="STATE_ID" low="0" high="7"/>
</reg32>
<reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-">
<bitfield name="STATE_ID" low="0" high="7"/>
</reg32>
<reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-">
<bitfield name="STATE_ID" low="16" high="23"/>
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
</reg32>
<reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
<doc>
This register clears pending loads queued up by