amd/addrlib: expose HTILE address equations to drivers on GFX10+

Similar to the DCC address equations. Only GFX10+ because this
is for copying VRS rates to the HTILE buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
This commit is contained in:
Samuel Pitoiset 2021-04-05 16:13:34 +02:00 committed by Marge Bot
parent 3ebe604ad6
commit 4d25229c24
2 changed files with 12 additions and 0 deletions

View File

@ -2785,6 +2785,10 @@ typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information
struct {
UINT_16* gfx10_bits; /* 72 2-byte elements */
} equation;
} ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
/**

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@ -252,6 +252,14 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeHtileInfo(
pOut->pMipInfo[0].sliceSize = pOut->sliceSize;
}
}
// Get the HTILE address equation (copied from HtileAddrFromCoord).
// Note that HTILE doesn't depend on the number of samples.
const UINT_32 index = m_xmaskBaseIndex;
const UINT_8* patIdxTable = m_settings.supportRbPlus ? GFX10_HTILE_RBPLUS_PATIDX : GFX10_HTILE_PATIDX;
ADDR_C_ASSERT(sizeof(GFX10_HTILE_SW_PATTERN[patIdxTable[index]]) == 72 * 2);
pOut->equation.gfx10_bits = (UINT_16 *)GFX10_HTILE_SW_PATTERN[patIdxTable[index]];
}
return ret;