nir: add is_gather_implicit_lod

Needed for SPV_AMD_texture_gather_bias_lod.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22315>

src/compiler/nir/nir.h

@@ -2321,6 +2321,9 @@ typedef struct {
    /** Validation needs to know this for gradient component count */
    unsigned array_is_lowered_cube : 1;
 
+   /** True if this tg4 instruction has an implicit LOD or LOD bias, instead of using level 0 */
+   unsigned is_gather_implicit_lod : 1;
+
    /** Gather offsets */
    int8_t tg4_offsets[4][2];
 

src/compiler/nir/nir_lower_tex.c

@@ -1160,6 +1160,7 @@ lower_tg4_offsets(nir_builder *b, nir_tex_instr *tex)
       tex_copy->is_shadow = tex->is_shadow;
       tex_copy->is_new_style_shadow = tex->is_new_style_shadow;
       tex_copy->is_sparse = tex->is_sparse;
+      tex_copy->is_gather_implicit_lod = tex->is_gather_implicit_lod;
       tex_copy->component = tex->component;
       tex_copy->dest_type = tex->dest_type;
 

src/compiler/nir/nir_print.c

@@ -1401,6 +1401,9 @@ print_tex_instr(nir_tex_instr *instr, print_state *state)
       }
    }
 
+   if (instr->is_gather_implicit_lod)
+      fprintf(fp, ", implicit lod");
+
    if (instr->op == nir_texop_tg4) {
       fprintf(fp, ", %u (gather_component)", instr->component);
    }

src/compiler/nir/nir_serialize.c

@@ -1502,7 +1502,8 @@ union packed_tex_data {
       unsigned texture_non_uniform:1;
       unsigned sampler_non_uniform:1;
       unsigned array_is_lowered_cube:1;
-      unsigned unused:6; /* Mark unused for valgrind. */
+      unsigned is_gather_implicit_lod:1;
+      unsigned unused:5; /* Mark unused for valgrind. */
    } u;
 };
 
@@ -1539,6 +1540,7 @@ write_tex(write_ctx *ctx, const nir_tex_instr *tex)
       .u.texture_non_uniform = tex->texture_non_uniform,
       .u.sampler_non_uniform = tex->sampler_non_uniform,
       .u.array_is_lowered_cube = tex->array_is_lowered_cube,
+      .u.is_gather_implicit_lod = tex->is_gather_implicit_lod,
    };
    blob_write_uint32(ctx->blob, packed.u32);
 
@@ -1576,6 +1578,7 @@ read_tex(read_ctx *ctx, union packed_instr header)
    tex->texture_non_uniform = packed.u.texture_non_uniform;
    tex->sampler_non_uniform = packed.u.sampler_non_uniform;
    tex->array_is_lowered_cube = packed.u.array_is_lowered_cube;
+   tex->is_gather_implicit_lod = packed.u.is_gather_implicit_lod;
 
    for (unsigned i = 0; i < tex->num_srcs; i++) {
       union packed_src src = read_src(ctx, &tex->src[i].src);

src/compiler/nir/nir_validate.c

@@ -981,6 +981,9 @@ validate_tex_instr(nir_tex_instr *instr, validate_state *state)
       validate_assert(state, !src_type_seen[nir_tex_src_offset]);
    }
 
+   if (instr->is_gather_implicit_lod)
+      validate_assert(state, instr->op == nir_texop_tg4);
+
    validate_dest(&instr->dest, state, 0, nir_tex_instr_dest_size(instr));
 
    unsigned bit_size = nir_alu_type_get_type_size(instr->dest_type);