mirrors/mesa
0
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2024-11-23 18:24:13 +08:00
Code Issues Packages Projects Releases Wiki Activity

amd: remove support for LLVM 3.9

Browse Source 
Only these are supported:
- LLVM 4.0
- LLVM 5.0
- LLVM 6.0
- master (7.0)

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2018-02-02 19:26:49 +01:00
parent c75a4e5b46
commit 3bf1e036e8
12 changed files with 74 additions and 241 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
configure.ac
View File

@ -103,8 +103,8 @@ dnl LLVM versions
LLVM_REQUIRED_GALLIUM=3.3.0
LLVM_REQUIRED_OPENCL=3.9.0
LLVM_REQUIRED_R600=3.9.0
LLVM_REQUIRED_RADEONSI=3.9.0
LLVM_REQUIRED_RADV=3.9.0
LLVM_REQUIRED_RADEONSI=4.0.0
LLVM_REQUIRED_RADV=4.0.0
LLVM_REQUIRED_SWR=3.9.0
dnl Check for progs

6
meson.build
View File

@ -992,9 +992,9 @@ if with_gallium_opencl
# TODO: optional modules
endif
if with_amd_vk
if with_amd_vk or with_gallium_radeonsi
_llvm_version = '>= 4.0.0'
elif with_gallium_opencl or with_gallium_swr or with_gallium_r600 or with_gallium_radeonsi
elif with_gallium_opencl or with_gallium_swr or with_gallium_r600
_llvm_version = '>= 3.9.0'
else
_llvm_version = '>= 3.3.0'
@ -1031,7 +1031,7 @@ if with_llvm
'-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
]
elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM is disabled.')
error('The following drivers require LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM is disabled.')
endif
dep_glvnd = []

185
src/amd/common/ac_llvm_build.c
View File

@ -220,8 +220,7 @@ ac_build_intrinsic(struct ac_llvm_context *ctx, const char *name,
unsigned param_count, unsigned attrib_mask)
{
LLVMValueRef function, call;
bool set_callsite_attrs = HAVE_LLVM >= 0x0400 &&
!(attrib_mask & AC_FUNC_ATTR_LEGACY);
bool set_callsite_attrs = !(attrib_mask & AC_FUNC_ATTR_LEGACY);
function = LLVMGetNamedFunction(ctx->module, name);
if (!function) {
@ -721,20 +720,6 @@ ac_build_fs_interp(struct ac_llvm_context *ctx,
{
LLVMValueRef args[5];
LLVMValueRef p1;
if (HAVE_LLVM < 0x0400) {
LLVMValueRef ij[2];
ij[0] = LLVMBuildBitCast(ctx->builder, i, ctx->i32, "");
ij[1] = LLVMBuildBitCast(ctx->builder, j, ctx->i32, "");
args[0] = llvm_chan;
args[1] = attr_number;
args[2] = params;
args[3] = ac_build_gather_values(ctx, ij, 2);
return ac_build_intrinsic(ctx, "llvm.SI.fs.interp",
ctx->f32, args, 4,
AC_FUNC_ATTR_READNONE);
}
args[0] = i;
args[1] = llvm_chan;
@ -762,16 +747,6 @@ ac_build_fs_interp_mov(struct ac_llvm_context *ctx,
LLVMValueRef params)
{
LLVMValueRef args[4];
if (HAVE_LLVM < 0x0400) {
args[0] = llvm_chan;
args[1] = attr_number;
args[2] = params;
return ac_build_intrinsic(ctx,
"llvm.SI.fs.constant",
ctx->f32, args, 3,
AC_FUNC_ATTR_READNONE);
}
args[0] = parameter;
args[1] = llvm_chan;
@ -1209,10 +1184,9 @@ ac_build_sendmsg(struct ac_llvm_context *ctx,
LLVMValueRef wave_id)
{
LLVMValueRef args[2];
const char *intr_name = (HAVE_LLVM < 0x0400) ? "llvm.SI.sendmsg" : "llvm.amdgcn.s.sendmsg";
args[0] = LLVMConstInt(ctx->i32, msg, false);
args[1] = wave_id;
ac_build_intrinsic(ctx, intr_name, ctx->voidt, args, 2, 0);
ac_build_intrinsic(ctx, "llvm.amdgcn.s.sendmsg", ctx->voidt, args, 2, 0);
}
LLVMValueRef
@ -1220,9 +1194,7 @@ ac_build_imsb(struct ac_llvm_context *ctx,
LLVMValueRef arg,
LLVMTypeRef dst_type)
{
const char *intr_name = (HAVE_LLVM < 0x0400) ? "llvm.AMDGPU.flbit.i32" :
"llvm.amdgcn.sffbh.i32";
LLVMValueRef msb = ac_build_intrinsic(ctx, intr_name,
LLVMValueRef msb = ac_build_intrinsic(ctx, "llvm.amdgcn.sffbh.i32",
dst_type, &arg, 1,
AC_FUNC_ATTR_READNONE);
@ -1370,124 +1342,58 @@ void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a)
LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
struct ac_image_args *a)
{
LLVMTypeRef dst_type;
LLVMValueRef args[11];
unsigned num_args = 0;
const char *name = NULL;
char intr_name[128], type[64];
if (HAVE_LLVM >= 0x0400) {
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
if (sample)
args[num_args++] = ac_to_float(ctx, a->addr);
else
args[num_args++] = a->addr;
if (sample)
args[num_args++] = ac_to_float(ctx, a->addr);
else
args[num_args++] = a->addr;
args[num_args++] = a->resource;
if (sample)
args[num_args++] = a->sampler;
args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
if (sample)
args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
args[num_args++] = ctx->i1false; /* glc */
args[num_args++] = ctx->i1false; /* slc */
args[num_args++] = ctx->i1false; /* lwe */
args[num_args++] = LLVMConstInt(ctx->i1, a->da, 0);
switch (a->opcode) {
case ac_image_sample:
name = "llvm.amdgcn.image.sample";
break;
case ac_image_gather4:
name = "llvm.amdgcn.image.gather4";
break;
case ac_image_load:
name = "llvm.amdgcn.image.load";
break;
case ac_image_load_mip:
name = "llvm.amdgcn.image.load.mip";
break;
case ac_image_get_lod:
name = "llvm.amdgcn.image.getlod";
break;
case ac_image_get_resinfo:
name = "llvm.amdgcn.image.getresinfo";
break;
default:
unreachable("invalid image opcode");
}
ac_build_type_name_for_intr(LLVMTypeOf(args[0]), type,
sizeof(type));
snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.v4f32.%s.v8i32",
name,
a->compare ? ".c" : "",
a->bias ? ".b" :
a->lod ? ".l" :
a->deriv ? ".d" :
a->level_zero ? ".lz" : "",
a->offset ? ".o" : "",
type);
LLVMValueRef result =
ac_build_intrinsic(ctx, intr_name,
ctx->v4f32, args, num_args,
AC_FUNC_ATTR_READNONE);
if (!sample) {
result = LLVMBuildBitCast(ctx->builder, result,
ctx->v4i32, "");
}
return result;
}
args[num_args++] = a->addr;
args[num_args++] = a->resource;
if (a->opcode == ac_image_load ||
a->opcode == ac_image_load_mip ||
a->opcode == ac_image_get_resinfo) {
dst_type = ctx->v4i32;
} else {
dst_type = ctx->v4f32;
if (sample)
args[num_args++] = a->sampler;
}
args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
args[num_args++] = LLVMConstInt(ctx->i32, a->unorm, 0);
args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
args[num_args++] = LLVMConstInt(ctx->i32, a->da, 0);
args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
if (sample)
args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
args[num_args++] = ctx->i1false; /* glc */
args[num_args++] = ctx->i1false; /* slc */
args[num_args++] = ctx->i1false; /* lwe */
args[num_args++] = LLVMConstInt(ctx->i1, a->da, 0);
switch (a->opcode) {
case ac_image_sample:
name = "llvm.SI.image.sample";
name = "llvm.amdgcn.image.sample";
break;
case ac_image_gather4:
name = "llvm.SI.gather4";
name = "llvm.amdgcn.image.gather4";
break;
case ac_image_load:
name = "llvm.SI.image.load";
name = "llvm.amdgcn.image.load";
break;
case ac_image_load_mip:
name = "llvm.SI.image.load.mip";
name = "llvm.amdgcn.image.load.mip";
break;
case ac_image_get_lod:
name = "llvm.SI.getlod";
name = "llvm.amdgcn.image.getlod";
break;
case ac_image_get_resinfo:
name = "llvm.SI.getresinfo";
name = "llvm.amdgcn.image.getresinfo";
break;
default:
unreachable("invalid image opcode");
}
ac_build_type_name_for_intr(LLVMTypeOf(a->addr), type, sizeof(type));
snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.%s",
ac_build_type_name_for_intr(LLVMTypeOf(args[0]), type,
sizeof(type));
snprintf(intr_name, sizeof(intr_name), "%s%s%s%s.v4f32.%s.v8i32",
name,
a->compare ? ".c" : "",
a->bias ? ".b" :
@ -1497,10 +1403,15 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
a->offset ? ".o" : "",
type);
return ac_build_intrinsic(ctx, intr_name,
dst_type, args, num_args,
AC_FUNC_ATTR_READNONE |
AC_FUNC_ATTR_LEGACY);
LLVMValueRef result =
ac_build_intrinsic(ctx, intr_name,
ctx->v4f32, args, num_args,
AC_FUNC_ATTR_READNONE);
if (!sample) {
result = LLVMBuildBitCast(ctx->builder, result,
ctx->v4i32, "");
}
return result;
}
LLVMValueRef ac_build_cvt_pkrtz_f16(struct ac_llvm_context *ctx,
@ -1738,19 +1649,15 @@ void ac_get_image_intr_name(const char *base_name,
ac_build_type_name_for_intr(coords_type, coords_type_name,
sizeof(coords_type_name));
if (HAVE_LLVM <= 0x0309) {
snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
} else {
char data_type_name[8];
char rsrc_type_name[8];
char data_type_name[8];
char rsrc_type_name[8];
ac_build_type_name_for_intr(data_type, data_type_name,
sizeof(data_type_name));
ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
sizeof(rsrc_type_name));
snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
data_type_name, coords_type_name, rsrc_type_name);
}
ac_build_type_name_for_intr(data_type, data_type_name,
sizeof(data_type_name));
ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
sizeof(rsrc_type_name));
snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
data_type_name, coords_type_name, rsrc_type_name);
}
#define AC_EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)

10
src/amd/common/ac_llvm_helper.cpp
View File

@ -65,20 +65,12 @@ bool ac_is_sgpr_param(LLVMValueRef arg)
LLVMValueRef ac_llvm_get_called_value(LLVMValueRef call)
{
#if HAVE_LLVM >= 0x0309
return LLVMGetCalledValue(call);
#else
return llvm::wrap(llvm::CallSite(llvm::unwrap<llvm::Instruction>(call)).getCalledValue());
#endif
}
bool ac_llvm_is_function(LLVMValueRef v)
{
#if HAVE_LLVM >= 0x0309
return LLVMGetValueKind(v) == LLVMFunctionValueKind;
#else
return llvm::isa<llvm::Function>(llvm::unwrap(v));
#endif
}
LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
@ -86,7 +78,6 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
{
LLVMBuilderRef builder = LLVMCreateBuilderInContext(ctx);
#if HAVE_LLVM >= 0x0308
llvm::FastMathFlags flags;
switch (float_mode) {
@ -105,7 +96,6 @@ LLVMBuilderRef ac_create_builder(LLVMContextRef ctx,
llvm::unwrap(builder)->setFastMathFlags(flags);
break;
}
#endif
return builder;
}

39
src/amd/common/ac_llvm_util.c
View File

@ -46,12 +46,11 @@ static void ac_init_llvm_target()
/* Workaround for bug in llvm 4.0 that causes image intrinsics
* to disappear.
* https://reviews.llvm.org/D26348
*
* "mesa" is the prefix for error messages.
*/
if (HAVE_LLVM >= 0x0400) {
/* "mesa" is the prefix for error messages */
const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
LLVMParseCommandLineOptions(2, argv, NULL);
}
const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
LLVMParseCommandLineOptions(2, argv, NULL);
}
static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
@ -146,25 +145,6 @@ LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum ac
return tm;
}
#if HAVE_LLVM < 0x0400
static LLVMAttribute ac_attr_to_llvm_attr(enum ac_func_attr attr)
{
switch (attr) {
case AC_FUNC_ATTR_ALWAYSINLINE: return LLVMAlwaysInlineAttribute;
case AC_FUNC_ATTR_INREG: return LLVMInRegAttribute;
case AC_FUNC_ATTR_NOALIAS: return LLVMNoAliasAttribute;
case AC_FUNC_ATTR_NOUNWIND: return LLVMNoUnwindAttribute;
case AC_FUNC_ATTR_READNONE: return LLVMReadNoneAttribute;
case AC_FUNC_ATTR_READONLY: return LLVMReadOnlyAttribute;
default:
fprintf(stderr, "Unhandled function attribute: %x\n", attr);
return 0;
}
}
#else
static const char *attr_to_str(enum ac_func_attr attr)
{
switch (attr) {
@ -183,20 +163,10 @@ static const char *attr_to_str(enum ac_func_attr attr)
}
}
#endif
void
ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
int attr_idx, enum ac_func_attr attr)
{
#if HAVE_LLVM < 0x0400
LLVMAttribute llvm_attr = ac_attr_to_llvm_attr(attr);
if (attr_idx == -1) {
LLVMAddFunctionAttr(function, llvm_attr);
} else {
LLVMAddAttribute(LLVMGetParam(function, attr_idx - 1), llvm_attr);
}
#else
const char *attr_name = attr_to_str(attr);
unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
strlen(attr_name));
@ -206,7 +176,6 @@ ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
else
LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
#endif
}
void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,

14
src/amd/common/ac_llvm_util.h
View File

@ -42,9 +42,9 @@ enum ac_func_attr {
AC_FUNC_ATTR_NOUNWIND = (1 << 4),
AC_FUNC_ATTR_READNONE = (1 << 5),
AC_FUNC_ATTR_READONLY = (1 << 6),
AC_FUNC_ATTR_WRITEONLY = HAVE_LLVM >= 0x0400 ? (1 << 7) : 0,
AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = HAVE_LLVM >= 0x0400 ? (1 << 8) : 0,
AC_FUNC_ATTR_CONVERGENT = HAVE_LLVM >= 0x0400 ? (1 << 9) : 0,
AC_FUNC_ATTR_WRITEONLY = (1 << 7),
AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = (1 << 8),
AC_FUNC_ATTR_CONVERGENT = (1 << 9),
/* Legacy intrinsic that needs attributes on function declarations
* and they must match the internal LLVM definition exactly, otherwise
@ -94,16 +94,14 @@ ac_get_load_intr_attribs(bool can_speculate)
{
/* READNONE means writes can't affect it, while READONLY means that
* writes can affect it. */
return can_speculate && HAVE_LLVM >= 0x0400 ?
AC_FUNC_ATTR_READNONE :
AC_FUNC_ATTR_READONLY;
return can_speculate ? AC_FUNC_ATTR_READNONE :
AC_FUNC_ATTR_READONLY;
}
static inline unsigned
ac_get_store_intr_attribs(bool writeonly_memory)
{
return writeonly_memory && HAVE_LLVM >= 0x0400 ?
AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
return writeonly_memory ? AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
AC_FUNC_ATTR_WRITEONLY;
}

32
src/amd/common/ac_nir_to_llvm.c
View File

@ -3635,18 +3635,10 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
params[0] = get_image_coords(ctx, instr);
params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
if (HAVE_LLVM <= 0x0309) {
params[3] = ctx->ac.i1false; /* r128 */
params[4] = da;
params[5] = glc;
params[6] = slc;
} else {
LLVMValueRef lwe = ctx->ac.i1false;
params[3] = glc;
params[4] = slc;
params[5] = lwe;
params[6] = da;
}
params[3] = glc;
params[4] = slc;
params[5] = ctx->ac.i1false;
params[6] = da;
ac_get_image_intr_name("llvm.amdgcn.image.load",
ctx->ac.v4f32, /* vdata */
@ -3694,18 +3686,10 @@ static void visit_image_store(struct ac_nir_context *ctx,
params[1] = get_image_coords(ctx, instr); /* coords */
params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
if (HAVE_LLVM <= 0x0309) {
params[4] = ctx->ac.i1false; /* r128 */
params[5] = da;
params[6] = glc;
params[7] = slc;
} else {
LLVMValueRef lwe = ctx->ac.i1false;
params[4] = glc;
params[5] = slc;
params[6] = lwe;
params[7] = da;
}
params[4] = glc;
params[5] = slc;
params[6] = ctx->ac.i1false;
params[7] = da;
ac_get_image_intr_name("llvm.amdgcn.image.store",
LLVMTypeOf(params[0]), /* vdata */

4
src/amd/vulkan/radv_device.c
View File

@ -1113,11 +1113,7 @@ VkResult radv_CreateDevice(
device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
#endif
#if HAVE_LLVM < 0x0400
device->llvm_supports_spill = false;
#else
device->llvm_supports_spill = true;
#endif
/* The maximum number of scratch waves. Scratch space isn't divided
* evenly between CUs. The number is only a function of the number of CUs.

3
src/gallium/drivers/radeonsi/si_compute.c
View File

@ -159,8 +159,7 @@ static void *si_create_compute_state(
program->local_size = cso->req_local_mem;
program->private_size = cso->req_private_mem;
program->input_size = cso->req_input_mem;
program->use_code_object_v2 = HAVE_LLVM >= 0x0400 &&
cso->ir_type == PIPE_SHADER_IR_NATIVE;
program->use_code_object_v2 = cso->ir_type == PIPE_SHADER_IR_NATIVE;
if (cso->ir_type == PIPE_SHADER_IR_TGSI) {
program->tokens = tgsi_dup_tokens(cso->prog);

13
src/gallium/drivers/radeonsi/si_get.c
View File

@ -188,10 +188,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
return 1;
case PIPE_CAP_TGSI_VOTE:
return HAVE_LLVM >= 0x0400;
return 1;
case PIPE_CAP_TGSI_BALLOT:
return HAVE_LLVM >= 0x0500;
@ -744,14 +742,9 @@ static int si_get_compute_param(struct pipe_screen *screen,
//TODO: select these params by asic
switch (param) {
case PIPE_COMPUTE_CAP_IR_TARGET: {
const char *gpu;
const char *triple;
if (HAVE_LLVM < 0x0400)
triple = "amdgcn--";
else
triple = "amdgcn-mesa-mesa3d";
const char *gpu, *triple;
triple = "amdgcn-mesa-mesa3d";
gpu = ac_get_llvm_processor_name(sscreen->info.family);
if (ret) {
sprintf(ret, "%s-%s", gpu, triple);

3
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
View File

@ -296,7 +296,7 @@ static void image_append_args(
LLVMValueRef slc = i1false;
LLVMValueRef lwe = i1false;
if (atomic || (HAVE_LLVM <= 0x0309)) {
if (atomic) {
emit_data->args[emit_data->arg_count++] = r128;
emit_data->args[emit_data->arg_count++] = da;
if (!atomic) {
@ -306,7 +306,6 @@ static void image_append_args(
return;
}
/* HAVE_LLVM >= 0x0400 */
emit_data->args[emit_data->arg_count++] = glc;
emit_data->args[emit_data->arg_count++] = slc;
emit_data->args[emit_data->arg_count++] = lwe;

2
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
View File

@ -1378,10 +1378,8 @@ void si_llvm_optimize_module(struct si_shader_context *ctx)
LLVMAddLICMPass(gallivm->passmgr);
LLVMAddAggressiveDCEPass(gallivm->passmgr);
LLVMAddCFGSimplificationPass(gallivm->passmgr);
#if HAVE_LLVM >= 0x0400
/* This is recommended by the instruction combining pass. */
LLVMAddEarlyCSEMemSSAPass(gallivm->passmgr);
#endif
LLVMAddInstructionCombiningPass(gallivm->passmgr);
/* Run the pass */