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intel: Move memory aligment information to intel_device_info

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This same information is also used in ANV, so intel_device_info is
a better place to have it.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21972>
This commit is contained in:
José Roberto de Souza 2023-03-14 12:34:36 -07:00 committed by Marge Bot
parent 12cf314dd8
commit 2ab3d5f436
3 changed files with 13 additions and 6 deletions
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7
src/gallium/drivers/iris/iris_bufmgr.c
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@ -226,7 +226,6 @@ struct iris_bufmgr {
struct util_vma_heap vma_allocator[IRIS_MEMZONE_COUNT]; struct util_vma_heap vma_allocator[IRIS_MEMZONE_COUNT];
uint64_t vma_min_align;
struct iris_memregion vram, sys; struct iris_memregion vram, sys;
/* Used only when use_global_vm is true. */ /* Used only when use_global_vm is true. */
@ -400,7 +399,7 @@ vma_alloc(struct iris_bufmgr *bufmgr,
/* Force minimum alignment based on device requirements */ /* Force minimum alignment based on device requirements */
assert((alignment & (alignment - 1)) == 0); assert((alignment & (alignment - 1)) == 0);
alignment = MAX2(alignment, bufmgr->vma_min_align); alignment = MAX2(alignment, bufmgr->devinfo.mem_alignment);
if (memzone == IRIS_MEMZONE_BORDER_COLOR_POOL) if (memzone == IRIS_MEMZONE_BORDER_COLOR_POOL)
return IRIS_BORDER_COLOR_POOL_ADDRESS; return IRIS_BORDER_COLOR_POOL_ADDRESS;
@ -2250,10 +2249,6 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
bufmgr->handle_table = bufmgr->handle_table =
_mesa_hash_table_create(NULL, _mesa_hash_uint, _mesa_key_uint_equal); _mesa_hash_table_create(NULL, _mesa_hash_uint, _mesa_key_uint_equal);
bufmgr->vma_min_align =
devinfo->verx10 >= 125 ? 2 * 1024 * 1024 :
(devinfo->has_local_mem ? 64 * 1024 : PAGE_SIZE);
if (devinfo->has_aux_map) { if (devinfo->has_aux_map) {
bufmgr->aux_map_ctx = intel_aux_map_init(bufmgr, &aux_map_allocator, bufmgr->aux_map_ctx = intel_aux_map_init(bufmgr, &aux_map_allocator,
devinfo); devinfo);

7
src/intel/dev/i915/intel_device_info.c
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@ -610,5 +610,12 @@ bool intel_device_info_i915_get_info_from_fd(int fd, struct intel_device_info *d
if (getparam(fd, I915_PARAM_HAS_CONTEXT_ISOLATION, &val)) if (getparam(fd, I915_PARAM_HAS_CONTEXT_ISOLATION, &val))
devinfo->has_context_isolation = val; devinfo->has_context_isolation = val;
if (devinfo->verx10 >= 125)
devinfo->mem_alignment = 2 * 1024 * 1024;
else if (devinfo->has_local_mem)
devinfo->mem_alignment = 64 * 1024;
else
devinfo->mem_alignment = 4096;
return true; return true;
} }

5
src/intel/dev/intel_device_info.h
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@ -383,6 +383,11 @@ struct intel_device_info
*/ */
unsigned engine_class_prefetch[INTEL_ENGINE_CLASS_COMPUTE + 1]; unsigned engine_class_prefetch[INTEL_ENGINE_CLASS_COMPUTE + 1];
/**
* Memory alignment requirement for this device.
*/
unsigned mem_alignment;
/** /**
* For the longest time the timestamp frequency for Gen's timestamp counter * For the longest time the timestamp frequency for Gen's timestamp counter
* could be assumed to be 12.5MHz, where the least significant bit neatly * could be assumed to be 12.5MHz, where the least significant bit neatly