diff --git a/docs/drivers/freedreno/hw/lrz.rst b/docs/drivers/freedreno/hw/lrz.rst index 8da4789a602..dc9a81ed3c4 100644 --- a/docs/drivers/freedreno/hw/lrz.rst +++ b/docs/drivers/freedreno/hw/lrz.rst @@ -95,6 +95,21 @@ This way it's always valid to fast-clear. On A7XX, the original depth clear value can be specified exactly allowing for fast-clear to any value rather than just ``1.0`` or ``0.0``. +LRZ Feedback +------------- + +Some draws do write depth but cannot contribute to LRZ during the BINNING pass +e.g. when fragment shader has "discard" in it, however they can contribute to LRZ +during the RENDERING pass via LRZ feedback mechanism. This may allow the draws +that follow to depth test against the updated LRZ, this is especially important +if such "bad" draws were at the start of the renderpass. + +LRZ feedback happens during the RENDERING pass when ``LRZ_FEEDBACK_ZMODE_MASK`` +is set, if draw has a6xx_ztest_mode that has corresponding flag set in +``LRZ_FEEDBACK_ZMODE_MASK`` - its depth values would be used for feedback. + +LRZ feedback alongside with LRZ testing also works during sysmem rendering. + LRZ Precision ------------- diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index e4f1b631822..b7753907f38 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -5367,7 +5367,7 @@ clusters: 00000000 GRAS_GS_LAYER_CNTL: { 0 } 00000000 GRAS_DS_LAYER_CNTL: { 0 } 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - 00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 GRAS_SAMPLE_CONFIG: { 0 } @@ -5610,7 +5610,7 @@ clusters: 00000000 GRAS_GS_LAYER_CNTL: { 0 } 00000000 GRAS_DS_LAYER_CNTL: { 0 } 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - 00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00000101 GRAS_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 GRAS_SAMPLE_CONFIG: { 0 } @@ -5705,7 +5705,7 @@ clusters: 00000000 GRAS_2D_RESOLVE_CNTL_2: { X = 0 | Y = 0 } - cluster-name: CLUSTER_PS - context: 0 - 00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 } 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } @@ -5882,7 +5882,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910) 00000000 0x8c32: 00000000 00000000 0x8c33: 00000000 - context: 1 - 00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00000101 RB_BIN_CONTROL: { BINW = 32 | BINH = 16 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0 } 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log index dcd316560a8..56a1f8bb113 100644 --- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log +++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log @@ -2294,7 +2294,7 @@ got cmdszdw=83 + 00000001 UCHE_UNKNOWN_0E12: 0x1 + 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 } -!+ 00e00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } +!+ 00e00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } + 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 0040003e GRAS_SC_WINDOW_SCISSOR_BR: { X = 62 | Y = 64 } @@ -2305,7 +2305,7 @@ got cmdszdw=83 + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } !+ 0040003e GRAS_2D_RESOLVE_CNTL_2: { X = 62 | Y = 64 } + 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS } -!+ 00e00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } +!+ 00e00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } + 00000000 RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_DISABLE | DITHER_MODE_MRT1 = DITHER_DISABLE | DITHER_MODE_MRT2 = DITHER_DISABLE | DITHER_MODE_MRT3 = DITHER_DISABLE | DITHER_MODE_MRT4 = DITHER_DISABLE | DITHER_MODE_MRT5 = DITHER_DISABLE | DITHER_MODE_MRT6 = DITHER_DISABLE | DITHER_MODE_MRT7 = DITHER_DISABLE } + 00000010 RB_UNKNOWN_8811: 0x1 + 00000000 RB_UNKNOWN_8818: 0 @@ -17195,7 +17195,7 @@ clusters: 00000000 GRAS_GS_LAYER_CNTL: { 0 } 00000000 GRAS_DS_LAYER_CNTL: { 0 } 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - 00e00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00e00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } 00000000 GRAS_SAMPLE_CONFIG: { 0 } @@ -17438,7 +17438,7 @@ clusters: 00000000 GRAS_GS_LAYER_CNTL: { 0 } 00000000 GRAS_DS_LAYER_CNTL: { 0 } 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - 00e00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00e00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } 00000000 GRAS_SAMPLE_CONFIG: { 0 } @@ -17533,7 +17533,7 @@ clusters: 0040003e GRAS_2D_RESOLVE_CNTL_2: { X = 62 | Y = 64 } - cluster-name: CLUSTER_PS - context: 0 - 00e00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00e00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00050010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x5 } 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } @@ -17710,7 +17710,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910) 00000000 0x8c32: 00000000 00000000 0x8c33: 00000000 - context: 1 - 00e00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00e00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00050010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x5 } 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log index afb7a1cd048..b0fe6979a47 100644 --- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log +++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log @@ -2538,7 +2538,7 @@ got cmdszdw=438 + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 } + 00000000 GRAS_VS_LAYER_CNTL: { 0 } !+ 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } -!+ 00c00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } +!+ 00c00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } + 00000000 GRAS_SAMPLE_CONFIG: { 0 } + 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } @@ -2553,7 +2553,7 @@ got cmdszdw=438 + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } !+ 003f003f GRAS_2D_RESOLVE_CNTL_2: { X = 63 | Y = 63 } !+ 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS } -!+ 00c00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } +!+ 00c00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } + 00000000 RB_SAMPLE_CONFIG: { 0 } !+ 00000010 RB_UNKNOWN_8811: 0x1 + 00000000 RB_UNKNOWN_8818: 0 @@ -151174,7 +151174,7 @@ clusters: 00000000 GRAS_GS_LAYER_CNTL: { 0 } 00000000 GRAS_DS_LAYER_CNTL: { 0 } 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - 00c00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00c00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } 00000000 GRAS_SAMPLE_CONFIG: { 0 } @@ -151417,7 +151417,7 @@ clusters: 00000000 GRAS_GS_LAYER_CNTL: { 0 } 00000000 GRAS_DS_LAYER_CNTL: { 0 } 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - 00c00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00c00000 GRAS_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } 00000000 GRAS_SAMPLE_CONFIG: { 0 } @@ -151512,7 +151512,7 @@ clusters: 003f003f GRAS_2D_RESOLVE_CNTL_2: { X = 63 | Y = 63 } - cluster-name: CLUSTER_PS - context: 0 - 00c00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00c00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00010010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 } 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } @@ -151689,7 +151689,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910) 00000000 0x8c32: 00000000 00000000 0x8c33: 00000000 - context: 1 - 00c00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = 0 } + 00c00000 RB_BIN_CONTROL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } 00010010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 } 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE } diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 5d164f2ebaf..e255cd6f4d1 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -3730,13 +3730,28 @@ to upconvert to 32b float internally? + + + + + + + + + + Disable LRZ feedback writes - + + Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have + GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. + In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. + + @@ -3992,7 +4007,7 @@ to upconvert to 32b float internally? - + @@ -4000,7 +4015,7 @@ to upconvert to 32b float internally? - + diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index f6ef5a4a53e..59807b244f7 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -504,7 +504,7 @@ struct tu_bin_size_params { enum a6xx_render_mode render_mode; bool force_lrz_write_dis; enum a6xx_buffers_location buffers_location; - unsigned lrz_feedback_zmode_mask; + enum a6xx_lrz_feedback_mask lrz_feedback_zmode_mask; }; template @@ -1860,7 +1860,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, .render_mode = RENDERING_PASS, .force_lrz_write_dis = true, .buffers_location = BUFFERS_IN_SYSMEM, - .lrz_feedback_zmode_mask = 0x0, + .lrz_feedback_zmode_mask = LRZ_FEEDBACK_NONE, }); if (CHIP == A7XX) { @@ -1952,7 +1952,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, { .render_mode = BINNING_PASS, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true); @@ -1964,7 +1964,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, .render_mode = RENDERING_PASS, .force_lrz_write_dis = true, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); tu_cs_emit_regs(cs, @@ -1986,8 +1986,9 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height, { .render_mode = RENDERING_PASS, + .force_lrz_write_dis = true, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); if (tiling->binning_possible) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc index f4db66ea53b..18c5558caf9 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc @@ -821,7 +821,7 @@ struct bin_size_params { enum a6xx_render_mode render_mode; bool force_lrz_write_dis; enum a6xx_buffers_location buffers_location; - unsigned lrz_feedback_zmode_mask; + enum a6xx_lrz_feedback_mask lrz_feedback_zmode_mask; }; template @@ -1021,7 +1021,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt set_bin_size(ring, gmem, { .render_mode = BINNING_PASS, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); update_render_cntl(batch, pfb, true); emit_binning_pass(batch); @@ -1040,7 +1040,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt .render_mode = RENDERING_PASS, .force_lrz_write_dis = true, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1); @@ -1061,7 +1061,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt set_bin_size(ring, gmem, { .render_mode = RENDERING_PASS, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); } @@ -1139,7 +1139,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) set_bin_size(ring, gmem, { .render_mode = RENDERING_PASS, .buffers_location = BUFFERS_IN_GMEM, - .lrz_feedback_zmode_mask = 0x6, + .lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z), }); OUT_PKT7(ring, CP_SET_MODE, 1);