mirror of
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intel: Sync xe_drm.h
Sync xe_drm.h with commit 3b8183b7efad ("drm/xe/uapi: Be more specific
about the vm_bind prefetch region").
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26238>
This commit is contained in:
José Roberto de Souza
Marge Bot
parent
e4ffb2473b
commit
205c5874d4
@ -19,12 +19,12 @@ extern "C" {
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/**
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* DOC: uevent generated by xe on it's pci node.
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*
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* XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt
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* DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt
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* fails. The value supplied with the event is always "NEEDS_RESET".
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* Additional information supplied is tile id and gt id of the gt unit for
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* which reset has failed.
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*/
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#define XE_RESET_FAILED_UEVENT "DEVICE_STATUS"
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#define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS"
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/**
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* struct xe_user_extension - Base class for defining a chain of extensions
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@ -141,21 +141,22 @@ struct drm_xe_engine_class_instance {
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__u16 engine_instance;
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__u16 gt_id;
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__u16 rsvd;
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/** @pad: MBZ */
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__u16 pad;
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};
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/**
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* enum drm_xe_memory_class - Supported memory classes.
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*/
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enum drm_xe_memory_class {
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/** @XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
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XE_MEM_REGION_CLASS_SYSMEM = 0,
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/** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
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DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
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/**
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* @XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
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* @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
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* represents the memory that is local to the device, which we
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* call VRAM. Not valid on integrated platforms.
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*/
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XE_MEM_REGION_CLASS_VRAM
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DRM_XE_MEM_REGION_CLASS_VRAM
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};
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/**
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@ -215,7 +216,7 @@ struct drm_xe_query_mem_region {
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* always equal the @total_size, since all of it will be CPU
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* accessible.
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*
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* Note this is only tracked for XE_MEM_REGION_CLASS_VRAM
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* Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM
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* regions (for other types the value here will always equal
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* zero).
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*/
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@ -227,7 +228,7 @@ struct drm_xe_query_mem_region {
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* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
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* accounting. Without this the value here will always equal
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* zero. Note this is only currently tracked for
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* XE_MEM_REGION_CLASS_VRAM regions (for other types the value
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* DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value
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* here will always be zero).
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*/
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__u64 cpu_visible_used;
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@ -290,13 +291,13 @@ struct drm_xe_query_engine_cycles {
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};
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/**
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* struct drm_xe_query_mem_usage - describe memory regions and usage
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* struct drm_xe_query_mem_regions - describe memory regions
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*
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* If a query is made with a struct drm_xe_device_query where .query
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* is equal to DRM_XE_DEVICE_QUERY_MEM_USAGE, then the reply uses
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* struct drm_xe_query_mem_usage in .data.
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* is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses
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* struct drm_xe_query_mem_regions in .data.
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*/
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struct drm_xe_query_mem_usage {
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struct drm_xe_query_mem_regions {
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/** @num_regions: number of memory regions returned in @regions */
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__u32 num_regions;
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/** @pad: MBZ */
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@ -320,12 +321,12 @@ struct drm_xe_query_config {
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/** @pad: MBZ */
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__u32 pad;
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#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
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#define XE_QUERY_CONFIG_FLAGS 1
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#define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
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#define XE_QUERY_CONFIG_MIN_ALIGNMENT 2
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#define XE_QUERY_CONFIG_VA_BITS 3
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#define XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
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#define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
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#define DRM_XE_QUERY_CONFIG_FLAGS 1
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#define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
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#define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
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#define DRM_XE_QUERY_CONFIG_VA_BITS 3
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#define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
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/** @info: array of elements containing the config info */
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__u64 info[];
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};
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@ -339,8 +340,8 @@ struct drm_xe_query_config {
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* implementing graphics and/or media operations.
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*/
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struct drm_xe_query_gt {
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#define XE_QUERY_GT_TYPE_MAIN 0
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#define XE_QUERY_GT_TYPE_MEDIA 1
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#define DRM_XE_QUERY_GT_TYPE_MAIN 0
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#define DRM_XE_QUERY_GT_TYPE_MEDIA 1
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/** @type: GT type: Main or Media */
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__u16 type;
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/** @gt_id: Unique ID of this GT within the PCI Device */
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@ -348,17 +349,18 @@ struct drm_xe_query_gt {
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/** @clock_freq: A clock frequency for timestamp */
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__u32 clock_freq;
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/**
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* @native_mem_regions: Bit mask of instances from
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* drm_xe_query_mem_usage that lives on the same GPU/Tile and have
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* direct access.
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* @near_mem_regions: Bit mask of instances from
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* drm_xe_query_mem_regions that is near the current engines of this GT.
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*/
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__u64 native_mem_regions;
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__u64 near_mem_regions;
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/**
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* @slow_mem_regions: Bit mask of instances from
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* drm_xe_query_mem_usage that this GT can indirectly access, although
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* they live on a different GPU/Tile.
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* @far_mem_regions: Bit mask of instances from
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* drm_xe_query_mem_regions that is far from the engines of this GT.
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* In general, it has extra indirections when compared to the
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* @near_mem_regions. For a discrete device this could mean system
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* memory and memory living in a different Tile.
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*/
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__u64 slow_mem_regions;
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__u64 far_mem_regions;
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/** @reserved: Reserved */
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__u64 reserved[8];
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};
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@ -400,7 +402,7 @@ struct drm_xe_query_topology_mask {
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* DSS_GEOMETRY ff ff ff ff 00 00 00 00
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* means 32 DSS are available for geometry.
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*/
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#define XE_TOPO_DSS_GEOMETRY (1 << 0)
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#define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0)
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/*
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* To query the mask of Dual Sub Slices (DSS) available for compute
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* operations. For example a query response containing the following
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@ -408,7 +410,7 @@ struct drm_xe_query_topology_mask {
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* DSS_COMPUTE ff ff ff ff 00 00 00 00
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* means 32 DSS are available for compute.
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*/
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#define XE_TOPO_DSS_COMPUTE (1 << 1)
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#define DRM_XE_TOPO_DSS_COMPUTE (1 << 1)
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/*
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* To query the mask of Execution Units (EU) available per Dual Sub
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* Slices (DSS). For example a query response containing the following
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@ -416,7 +418,7 @@ struct drm_xe_query_topology_mask {
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* EU_PER_DSS ff ff 00 00 00 00 00 00
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* means each DSS has 16 EU.
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*/
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#define XE_TOPO_EU_PER_DSS (1 << 2)
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#define DRM_XE_TOPO_EU_PER_DSS (1 << 2)
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/** @type: type of mask */
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__u16 type;
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@ -467,7 +469,7 @@ struct drm_xe_device_query {
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__u64 extensions;
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#define DRM_XE_DEVICE_QUERY_ENGINES 0
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#define DRM_XE_DEVICE_QUERY_MEM_USAGE 1
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#define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1
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#define DRM_XE_DEVICE_QUERY_CONFIG 2
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#define DRM_XE_DEVICE_QUERY_GT_LIST 3
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#define DRM_XE_DEVICE_QUERY_HWCONFIG 4
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@ -497,8 +499,8 @@ struct drm_xe_gem_create {
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*/
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__u64 size;
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#define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
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#define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
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#define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24)
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#define DRM_XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25)
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/*
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* When using VRAM as a possible placement, ensure that the corresponding VRAM
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* allocation will always use the CPU accessible part of VRAM. This is important
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@ -514,7 +516,7 @@ struct drm_xe_gem_create {
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* display surfaces, therefore the kernel requires setting this flag for such
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* objects, otherwise an error is thrown on small-bar systems.
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*/
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#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
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#define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26)
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/**
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* @flags: Flags, currently a mask of memory instances of where BO can
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* be placed
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@ -581,14 +583,14 @@ struct drm_xe_ext_set_property {
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};
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struct drm_xe_vm_create {
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#define XE_VM_EXTENSION_SET_PROPERTY 0
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#define DRM_XE_VM_EXTENSION_SET_PROPERTY 0
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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#define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0)
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#define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1)
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#define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2)
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#define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3)
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#define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0)
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#define DRM_XE_VM_CREATE_FLAG_COMPUTE_MODE (1 << 1)
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#define DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT (1 << 2)
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#define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 3)
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/** @flags: Flags */
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__u32 flags;
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@ -644,34 +646,38 @@ struct drm_xe_vm_bind_op {
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*/
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__u64 tile_mask;
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#define XE_VM_BIND_OP_MAP 0x0
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#define XE_VM_BIND_OP_UNMAP 0x1
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#define XE_VM_BIND_OP_MAP_USERPTR 0x2
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#define XE_VM_BIND_OP_UNMAP_ALL 0x3
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#define XE_VM_BIND_OP_PREFETCH 0x4
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#define DRM_XE_VM_BIND_OP_MAP 0x0
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#define DRM_XE_VM_BIND_OP_UNMAP 0x1
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#define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
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#define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
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#define DRM_XE_VM_BIND_OP_PREFETCH 0x4
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/** @op: Bind operation to perform */
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__u32 op;
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#define XE_VM_BIND_FLAG_READONLY (0x1 << 0)
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#define XE_VM_BIND_FLAG_ASYNC (0x1 << 1)
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#define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0)
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#define DRM_XE_VM_BIND_FLAG_ASYNC (1 << 1)
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/*
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* Valid on a faulting VM only, do the MAP operation immediately rather
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* than deferring the MAP to the page fault handler.
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*/
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#define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 2)
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#define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 2)
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/*
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* When the NULL flag is set, the page tables are setup with a special
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* bit which indicates writes are dropped and all reads return zero. In
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* the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP
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* the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP
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* operations, the BO handle MBZ, and the BO offset MBZ. This flag is
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* intended to implement VK sparse bindings.
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*/
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#define XE_VM_BIND_FLAG_NULL (0x1 << 3)
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#define DRM_XE_VM_BIND_FLAG_NULL (1 << 3)
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/** @flags: Bind flags */
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__u32 flags;
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/** @mem_region: Memory region to prefetch VMA to, instance not a mask */
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__u32 region;
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/**
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* @prefetch_mem_region_instance: Memory region to prefetch VMA to.
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* It is a region instance, not a mask.
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* To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation.
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*/
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__u32 prefetch_mem_region_instance;
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/** @reserved: Reserved */
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__u64 reserved[2];
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@ -721,19 +727,19 @@ struct drm_xe_vm_bind {
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__u64 reserved[2];
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};
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/* For use with XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY */
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/* For use with DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY */
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/* Monitor 128KB contiguous region with 4K sub-granularity */
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#define XE_ACC_GRANULARITY_128K 0
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#define DRM_XE_ACC_GRANULARITY_128K 0
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/* Monitor 2MB contiguous region with 64KB sub-granularity */
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#define XE_ACC_GRANULARITY_2M 1
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#define DRM_XE_ACC_GRANULARITY_2M 1
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/* Monitor 16MB contiguous region with 512KB sub-granularity */
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#define XE_ACC_GRANULARITY_16M 2
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#define DRM_XE_ACC_GRANULARITY_16M 2
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/* Monitor 64MB contiguous region with 2M sub-granularity */
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#define XE_ACC_GRANULARITY_64M 3
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#define DRM_XE_ACC_GRANULARITY_64M 3
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/**
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* struct drm_xe_exec_queue_set_property - exec queue set property
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@ -747,14 +753,14 @@ struct drm_xe_exec_queue_set_property {
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/** @exec_queue_id: Exec queue ID */
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__u32 exec_queue_id;
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#define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
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#define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
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#define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
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#define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3
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#define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4
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#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5
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#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6
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#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6
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#define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7
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/** @property: property to set */
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__u32 property;
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@ -766,7 +772,7 @@ struct drm_xe_exec_queue_set_property {
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};
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struct drm_xe_exec_queue_create {
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#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
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#define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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@ -805,7 +811,7 @@ struct drm_xe_exec_queue_get_property {
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/** @exec_queue_id: Exec queue ID */
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__u32 exec_queue_id;
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#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
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#define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
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/** @property: property to get */
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__u32 property;
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@ -831,11 +837,11 @@ struct drm_xe_sync {
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/** @extensions: Pointer to the first extension struct, if any */
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__u64 extensions;
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#define DRM_XE_SYNC_SYNCOBJ 0x0
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#define DRM_XE_SYNC_TIMELINE_SYNCOBJ 0x1
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#define DRM_XE_SYNC_DMA_BUF 0x2
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#define DRM_XE_SYNC_USER_FENCE 0x3
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#define DRM_XE_SYNC_SIGNAL 0x10
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#define DRM_XE_SYNC_FLAG_SYNCOBJ 0x0
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#define DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ 0x1
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#define DRM_XE_SYNC_FLAG_DMA_BUF 0x2
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#define DRM_XE_SYNC_FLAG_USER_FENCE 0x3
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#define DRM_XE_SYNC_FLAG_SIGNAL 0x10
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__u32 flags;
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/** @pad: MBZ */
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@ -912,17 +918,17 @@ struct drm_xe_wait_user_fence {
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*/
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__u64 addr;
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#define DRM_XE_UFENCE_WAIT_EQ 0
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#define DRM_XE_UFENCE_WAIT_NEQ 1
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#define DRM_XE_UFENCE_WAIT_GT 2
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#define DRM_XE_UFENCE_WAIT_GTE 3
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#define DRM_XE_UFENCE_WAIT_LT 4
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#define DRM_XE_UFENCE_WAIT_LTE 5
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#define DRM_XE_UFENCE_WAIT_OP_EQ 0x0
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#define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1
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#define DRM_XE_UFENCE_WAIT_OP_GT 0x2
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#define DRM_XE_UFENCE_WAIT_OP_GTE 0x3
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#define DRM_XE_UFENCE_WAIT_OP_LT 0x4
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#define DRM_XE_UFENCE_WAIT_OP_LTE 0x5
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/** @op: wait operation (type of comparison) */
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__u16 op;
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#define DRM_XE_UFENCE_WAIT_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
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#define DRM_XE_UFENCE_WAIT_ABSTIME (1 << 1)
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#define DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP (1 << 0) /* e.g. Wait on VM bind */
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#define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 1)
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/** @flags: wait flags */
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__u16 flags;
|
||||
|
||||
@ -932,18 +938,19 @@ struct drm_xe_wait_user_fence {
|
||||
/** @value: compare value */
|
||||
__u64 value;
|
||||
|
||||
#define DRM_XE_UFENCE_WAIT_U8 0xffu
|
||||
#define DRM_XE_UFENCE_WAIT_U16 0xffffu
|
||||
#define DRM_XE_UFENCE_WAIT_U32 0xffffffffu
|
||||
#define DRM_XE_UFENCE_WAIT_U64 0xffffffffffffffffu
|
||||
#define DRM_XE_UFENCE_WAIT_MASK_U8 0xffu
|
||||
#define DRM_XE_UFENCE_WAIT_MASK_U16 0xffffu
|
||||
#define DRM_XE_UFENCE_WAIT_MASK_U32 0xffffffffu
|
||||
#define DRM_XE_UFENCE_WAIT_MASK_U64 0xffffffffffffffffu
|
||||
/** @mask: comparison mask */
|
||||
__u64 mask;
|
||||
|
||||
/**
|
||||
* @timeout: how long to wait before bailing, value in nanoseconds.
|
||||
* Without DRM_XE_UFENCE_WAIT_ABSTIME flag set (relative timeout)
|
||||
* Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
|
||||
* it contains timeout expressed in nanoseconds to wait (fence will
|
||||
* expire at now() + timeout).
|
||||
* When DRM_XE_UFENCE_WAIT_ABSTIME flat is set (absolute timeout) wait
|
||||
* When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait
|
||||
* will end at timeout (uses system MONOTONIC_CLOCK).
|
||||
* Passing negative timeout leads to neverending wait.
|
||||
*
|
||||
@ -956,13 +963,13 @@ struct drm_xe_wait_user_fence {
|
||||
|
||||
/**
|
||||
* @num_engines: number of engine instances to wait on, must be zero
|
||||
* when DRM_XE_UFENCE_WAIT_SOFT_OP set
|
||||
* when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set
|
||||
*/
|
||||
__u64 num_engines;
|
||||
|
||||
/**
|
||||
* @instances: user pointer to array of drm_xe_engine_class_instance to
|
||||
* wait on, must be NULL when DRM_XE_UFENCE_WAIT_SOFT_OP set
|
||||
* wait on, must be NULL when DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP set
|
||||
*/
|
||||
__u64 instances;
|
||||
|
||||
@ -973,11 +980,11 @@ struct drm_xe_wait_user_fence {
|
||||
/**
|
||||
* DOC: XE PMU event config IDs
|
||||
*
|
||||
* Check 'man perf_event_open' to use the ID's XE_PMU_XXXX listed in xe_drm.h
|
||||
* Check 'man perf_event_open' to use the ID's DRM_XE_PMU_XXXX listed in xe_drm.h
|
||||
* in 'struct perf_event_attr' as part of perf_event_open syscall to read a
|
||||
* particular event.
|
||||
*
|
||||
* For example to open the XE_PMU_RENDER_GROUP_BUSY(0):
|
||||
* For example to open the DRMXE_PMU_RENDER_GROUP_BUSY(0):
|
||||
*
|
||||
* .. code-block:: C
|
||||
*
|
||||
@ -991,7 +998,7 @@ struct drm_xe_wait_user_fence {
|
||||
* attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED;
|
||||
* attr.use_clockid = 1;
|
||||
* attr.clockid = CLOCK_MONOTONIC;
|
||||
* attr.config = XE_PMU_RENDER_GROUP_BUSY(0);
|
||||
* attr.config = DRM_XE_PMU_RENDER_GROUP_BUSY(0);
|
||||
*
|
||||
* fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0);
|
||||
*/
|
||||
@ -999,15 +1006,15 @@ struct drm_xe_wait_user_fence {
|
||||
/*
|
||||
* Top bits of every counter are GT id.
|
||||
*/
|
||||
#define __XE_PMU_GT_SHIFT (56)
|
||||
#define __DRM_XE_PMU_GT_SHIFT (56)
|
||||
|
||||
#define ___XE_PMU_OTHER(gt, x) \
|
||||
(((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT))
|
||||
#define ___DRM_XE_PMU_OTHER(gt, x) \
|
||||
(((__u64)(x)) | ((__u64)(gt) << __DRM_XE_PMU_GT_SHIFT))
|
||||
|
||||
#define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 0)
|
||||
#define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1)
|
||||
#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2)
|
||||
#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
|
||||
#define DRM_XE_PMU_RENDER_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 0)
|
||||
#define DRM_XE_PMU_COPY_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 1)
|
||||
#define DRM_XE_PMU_MEDIA_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 2)
|
||||
#define DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 3)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
@ -80,7 +80,7 @@ iris_xe_init_batch(struct iris_bufmgr *bufmgr,
|
||||
.num_placements = count,
|
||||
};
|
||||
struct drm_xe_exec_queue_set_property exec_queue_property = {
|
||||
.property = XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
|
||||
.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
|
||||
.value = iris_context_priority_to_drm_sched_priority(priority),
|
||||
};
|
||||
int ret = intel_ioctl(iris_bufmgr_get_fd(bufmgr),
|
||||
|
||||
@ -31,7 +31,7 @@ bool
|
||||
iris_xe_init_global_vm(struct iris_bufmgr *bufmgr, uint32_t *vm_id)
|
||||
{
|
||||
struct drm_xe_vm_create create = {
|
||||
.flags = DRM_XE_VM_CREATE_SCRATCH_PAGE,
|
||||
.flags = DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE,
|
||||
};
|
||||
if (intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_IOCTL_XE_VM_CREATE, &create))
|
||||
return false;
|
||||
|
||||
@ -52,10 +52,10 @@ xe_gem_create(struct iris_bufmgr *bufmgr,
|
||||
* do not know what the process this is shared with will do with it
|
||||
*/
|
||||
if (alloc_flags & BO_ALLOC_SCANOUT)
|
||||
flags |= XE_GEM_CREATE_FLAG_SCANOUT;
|
||||
flags |= DRM_XE_GEM_CREATE_FLAG_SCANOUT;
|
||||
if (!intel_vram_all_mappable(iris_bufmgr_get_device_info(bufmgr)) &&
|
||||
heap_flags == IRIS_HEAP_DEVICE_LOCAL_PREFERRED)
|
||||
flags |= XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
|
||||
flags |= DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
|
||||
|
||||
struct drm_xe_gem_create gem_create = {
|
||||
.vm_id = vm_id,
|
||||
@ -89,7 +89,7 @@ xe_gem_mmap(struct iris_bufmgr *bufmgr, struct iris_bo *bo)
|
||||
static inline int
|
||||
xe_gem_vm_bind_op(struct iris_bo *bo, uint32_t op)
|
||||
{
|
||||
uint32_t handle = op == XE_VM_BIND_OP_UNMAP ? 0 : bo->gem_handle;
|
||||
uint32_t handle = op == DRM_XE_VM_BIND_OP_UNMAP ? 0 : bo->gem_handle;
|
||||
uint64_t range, obj_offset = 0;
|
||||
int ret;
|
||||
|
||||
@ -102,8 +102,8 @@ xe_gem_vm_bind_op(struct iris_bo *bo, uint32_t op)
|
||||
if (bo->real.userptr) {
|
||||
handle = 0;
|
||||
obj_offset = (uintptr_t)bo->real.map;
|
||||
if (op == XE_VM_BIND_OP_MAP)
|
||||
op = XE_VM_BIND_OP_MAP_USERPTR;
|
||||
if (op == DRM_XE_VM_BIND_OP_MAP)
|
||||
op = DRM_XE_VM_BIND_OP_MAP_USERPTR;
|
||||
}
|
||||
|
||||
struct drm_xe_vm_bind args = {
|
||||
@ -126,13 +126,13 @@ xe_gem_vm_bind_op(struct iris_bo *bo, uint32_t op)
|
||||
static bool
|
||||
xe_gem_vm_bind(struct iris_bo *bo)
|
||||
{
|
||||
return xe_gem_vm_bind_op(bo, XE_VM_BIND_OP_MAP) == 0;
|
||||
return xe_gem_vm_bind_op(bo, DRM_XE_VM_BIND_OP_MAP) == 0;
|
||||
}
|
||||
|
||||
static bool
|
||||
xe_gem_vm_unbind(struct iris_bo *bo)
|
||||
{
|
||||
return xe_gem_vm_bind_op(bo, XE_VM_BIND_OP_UNMAP) == 0;
|
||||
return xe_gem_vm_bind_op(bo, DRM_XE_VM_BIND_OP_UNMAP) == 0;
|
||||
}
|
||||
|
||||
static bool
|
||||
@ -160,7 +160,7 @@ xe_batch_check_for_reset(struct iris_batch *batch)
|
||||
enum pipe_reset_status status = PIPE_NO_RESET;
|
||||
struct drm_xe_exec_queue_get_property exec_queue_get_property = {
|
||||
.exec_queue_id = batch->xe.exec_queue_id,
|
||||
.property = XE_EXEC_QUEUE_GET_PROPERTY_BAN,
|
||||
.property = DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN,
|
||||
};
|
||||
int ret = intel_ioctl(iris_bufmgr_get_fd(batch->screen->bufmgr),
|
||||
DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY,
|
||||
@ -330,10 +330,10 @@ xe_batch_submit(struct iris_batch *batch)
|
||||
|
||||
util_dynarray_foreach(&batch->exec_fences, struct iris_batch_fence,
|
||||
fence) {
|
||||
uint32_t flags = DRM_XE_SYNC_SYNCOBJ;
|
||||
uint32_t flags = DRM_XE_SYNC_FLAG_SYNCOBJ;
|
||||
|
||||
if (fence->flags & IRIS_BATCH_FENCE_SIGNAL)
|
||||
flags |= DRM_XE_SYNC_SIGNAL;
|
||||
flags |= DRM_XE_SYNC_FLAG_SIGNAL;
|
||||
|
||||
syncs[i].handle = fence->handle;
|
||||
syncs[i].flags = flags;
|
||||
|
||||
@ -65,12 +65,12 @@ xe_query_config(int fd, struct intel_device_info *devinfo)
|
||||
if (!config)
|
||||
return false;
|
||||
|
||||
if (config->info[XE_QUERY_CONFIG_FLAGS] & XE_QUERY_CONFIG_FLAGS_HAS_VRAM)
|
||||
if (config->info[DRM_XE_QUERY_CONFIG_FLAGS] & DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM)
|
||||
devinfo->has_local_mem = true;
|
||||
|
||||
devinfo->revision = (config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] >> 16) & 0xFFFF;
|
||||
devinfo->gtt_size = 1ull << config->info[XE_QUERY_CONFIG_VA_BITS];
|
||||
devinfo->mem_alignment = config->info[XE_QUERY_CONFIG_MIN_ALIGNMENT];
|
||||
devinfo->revision = (config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] >> 16) & 0xFFFF;
|
||||
devinfo->gtt_size = 1ull << config->info[DRM_XE_QUERY_CONFIG_VA_BITS];
|
||||
devinfo->mem_alignment = config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT];
|
||||
|
||||
free(config);
|
||||
return true;
|
||||
@ -80,8 +80,8 @@ bool
|
||||
intel_device_info_xe_query_regions(int fd, struct intel_device_info *devinfo,
|
||||
bool update)
|
||||
{
|
||||
struct drm_xe_query_mem_usage *regions;
|
||||
regions = xe_query_alloc_fetch(fd, DRM_XE_DEVICE_QUERY_MEM_USAGE, NULL);
|
||||
struct drm_xe_query_mem_regions *regions;
|
||||
regions = xe_query_alloc_fetch(fd, DRM_XE_DEVICE_QUERY_MEM_REGIONS, NULL);
|
||||
if (!regions)
|
||||
return false;
|
||||
|
||||
@ -89,7 +89,7 @@ intel_device_info_xe_query_regions(int fd, struct intel_device_info *devinfo,
|
||||
struct drm_xe_query_mem_region *region = ®ions->regions[i];
|
||||
|
||||
switch (region->mem_class) {
|
||||
case XE_MEM_REGION_CLASS_SYSMEM: {
|
||||
case DRM_XE_MEM_REGION_CLASS_SYSMEM: {
|
||||
if (!update) {
|
||||
devinfo->mem.sram.mem.klass = region->mem_class;
|
||||
devinfo->mem.sram.mem.instance = region->instance;
|
||||
@ -102,7 +102,7 @@ intel_device_info_xe_query_regions(int fd, struct intel_device_info *devinfo,
|
||||
devinfo->mem.sram.mappable.free = region->total_size - region->used;
|
||||
break;
|
||||
}
|
||||
case XE_MEM_REGION_CLASS_VRAM: {
|
||||
case DRM_XE_MEM_REGION_CLASS_VRAM: {
|
||||
if (!update) {
|
||||
devinfo->mem.vram.mem.klass = region->mem_class;
|
||||
devinfo->mem.vram.mem.instance = region->instance;
|
||||
@ -138,7 +138,7 @@ xe_query_gts(int fd, struct intel_device_info *devinfo)
|
||||
return false;
|
||||
|
||||
for (uint32_t i = 0; i < gt_list->num_gt; i++) {
|
||||
if (gt_list->gt_list[i].type == XE_QUERY_GT_TYPE_MAIN)
|
||||
if (gt_list->gt_list[i].type == DRM_XE_QUERY_GT_TYPE_MAIN)
|
||||
devinfo->timestamp_frequency = gt_list->gt_list[i].clock_freq;
|
||||
}
|
||||
|
||||
@ -275,11 +275,11 @@ xe_query_topology(int fd, struct intel_device_info *devinfo)
|
||||
while (topology < end) {
|
||||
if (topology->gt_id == 0) {
|
||||
switch (topology->type) {
|
||||
case XE_TOPO_DSS_GEOMETRY:
|
||||
case DRM_XE_TOPO_DSS_GEOMETRY:
|
||||
geo_dss_mask = topology->mask;
|
||||
geo_dss_num_bytes = topology->num_bytes;
|
||||
break;
|
||||
case XE_TOPO_EU_PER_DSS:
|
||||
case DRM_XE_TOPO_EU_PER_DSS:
|
||||
eu_per_dss_mask = (uint32_t *)topology->mask;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -45,7 +45,7 @@ xe_execute_simple_batch(struct anv_queue *queue,
|
||||
return vk_errorf(device, VK_ERROR_UNKNOWN, "Unable to create sync obj");
|
||||
|
||||
struct drm_xe_sync sync = {
|
||||
.flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
|
||||
.flags = DRM_XE_SYNC_FLAG_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
|
||||
.handle = syncobj_handle,
|
||||
};
|
||||
struct drm_xe_exec exec = {
|
||||
@ -91,14 +91,14 @@ xe_exec_fill_sync(struct drm_xe_sync *xe_sync, struct vk_sync *vk_sync,
|
||||
xe_sync->handle = syncobj->syncobj;
|
||||
|
||||
if (value) {
|
||||
xe_sync->flags |= DRM_XE_SYNC_TIMELINE_SYNCOBJ;
|
||||
xe_sync->flags |= DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ;
|
||||
xe_sync->timeline_value = value;
|
||||
} else {
|
||||
xe_sync->flags |= DRM_XE_SYNC_SYNCOBJ;
|
||||
xe_sync->flags |= DRM_XE_SYNC_FLAG_SYNCOBJ;
|
||||
}
|
||||
|
||||
if (signal)
|
||||
xe_sync->flags |= DRM_XE_SYNC_SIGNAL;
|
||||
xe_sync->flags |= DRM_XE_SYNC_FLAG_SIGNAL;
|
||||
}
|
||||
|
||||
static VkResult
|
||||
@ -193,7 +193,7 @@ xe_execute_trtt_batch(struct anv_sparse_submission *submit,
|
||||
VkResult result;
|
||||
|
||||
struct drm_xe_sync extra_sync = {
|
||||
.flags = DRM_XE_SYNC_TIMELINE_SYNCOBJ | DRM_XE_SYNC_SIGNAL,
|
||||
.flags = DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ | DRM_XE_SYNC_FLAG_SIGNAL,
|
||||
.handle = trtt->timeline_handle,
|
||||
.timeline_value = trtt_bbo->timeline_val,
|
||||
};
|
||||
|
||||
@ -37,7 +37,7 @@ bool anv_xe_device_destroy_vm(struct anv_device *device)
|
||||
VkResult anv_xe_device_setup_vm(struct anv_device *device)
|
||||
{
|
||||
struct drm_xe_vm_create create = {
|
||||
.flags = DRM_XE_VM_CREATE_SCRATCH_PAGE,
|
||||
.flags = DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE,
|
||||
};
|
||||
if (intel_ioctl(device->fd, DRM_IOCTL_XE_VM_CREATE, &create) != 0)
|
||||
return vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
|
||||
@ -97,7 +97,7 @@ anv_xe_physical_device_get_parameters(struct anv_physical_device *device)
|
||||
|
||||
device->has_exec_timeline = true;
|
||||
device->max_context_priority =
|
||||
drm_sched_priority_to_vk_priority(config->info[XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY]);
|
||||
drm_sched_priority_to_vk_priority(config->info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY]);
|
||||
|
||||
free(config);
|
||||
return VK_SUCCESS;
|
||||
@ -163,7 +163,7 @@ anv_xe_get_device_status(struct anv_device *device, uint32_t exec_queue_id)
|
||||
VkResult result = VK_SUCCESS;
|
||||
struct drm_xe_exec_queue_get_property exec_queue_get_property = {
|
||||
.exec_queue_id = exec_queue_id,
|
||||
.property = XE_EXEC_QUEUE_GET_PROPERTY_BAN,
|
||||
.property = DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN,
|
||||
};
|
||||
int ret = intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY,
|
||||
&exec_queue_get_property);
|
||||
|
||||
@ -45,11 +45,11 @@ xe_gem_create(struct anv_device *device,
|
||||
|
||||
uint32_t flags = 0;
|
||||
if (alloc_flags & ANV_BO_ALLOC_SCANOUT)
|
||||
flags |= XE_GEM_CREATE_FLAG_SCANOUT;
|
||||
flags |= DRM_XE_GEM_CREATE_FLAG_SCANOUT;
|
||||
if ((alloc_flags & (ANV_BO_ALLOC_MAPPED | ANV_BO_ALLOC_LOCAL_MEM_CPU_VISIBLE)) &&
|
||||
!(alloc_flags & ANV_BO_ALLOC_NO_LOCAL_MEM) &&
|
||||
device->physical->vram_non_mappable.size > 0)
|
||||
flags |= XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
|
||||
flags |= DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
|
||||
|
||||
struct drm_xe_gem_create gem_create = {
|
||||
/* From xe_drm.h: If a VM is specified, this BO must:
|
||||
@ -132,20 +132,20 @@ xe_vm_bind_op(struct anv_device *device,
|
||||
.range = bind->size,
|
||||
.addr = intel_48b_address(bind->address),
|
||||
.tile_mask = 0,
|
||||
.op = XE_VM_BIND_OP_UNMAP,
|
||||
.op = DRM_XE_VM_BIND_OP_UNMAP,
|
||||
.flags = 0,
|
||||
.region = 0,
|
||||
.prefetch_mem_region_instance = 0,
|
||||
};
|
||||
|
||||
if (bind->op == ANV_VM_BIND) {
|
||||
if (!bo) {
|
||||
xe_bind->op = XE_VM_BIND_OP_MAP;
|
||||
xe_bind->flags |= XE_VM_BIND_FLAG_NULL;
|
||||
xe_bind->op = DRM_XE_VM_BIND_OP_MAP;
|
||||
xe_bind->flags |= DRM_XE_VM_BIND_FLAG_NULL;
|
||||
assert(xe_bind->obj_offset == 0);
|
||||
} else if (bo->from_host_ptr) {
|
||||
xe_bind->op = XE_VM_BIND_OP_MAP_USERPTR;
|
||||
xe_bind->op = DRM_XE_VM_BIND_OP_MAP_USERPTR;
|
||||
} else {
|
||||
xe_bind->op = XE_VM_BIND_OP_MAP;
|
||||
xe_bind->op = DRM_XE_VM_BIND_OP_MAP;
|
||||
xe_bind->obj = bo->gem_handle;
|
||||
}
|
||||
}
|
||||
|
||||
@ -118,7 +118,7 @@ create_engine(struct anv_device *device,
|
||||
|
||||
struct drm_xe_exec_queue_set_property exec_queue_property = {
|
||||
.exec_queue_id = create.exec_queue_id,
|
||||
.property = XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
|
||||
.property = DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
|
||||
.value = anv_vk_priority_to_drm_sched_priority(priority),
|
||||
};
|
||||
ret = intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user