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intel: Sync xe_drm.h

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Sync xe_drm.h with commit ebe27e42c0a2 ("drm/xe/uapi: support pat_index selection with vm_bind").

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462>
This commit is contained in:
José Roberto de Souza 2023-09-18 09:53:52 -07:00 committed by Marge Bot
parent 500e037661
commit 183fd14143
1 changed files with 64 additions and 6 deletions
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70
include/drm-uapi/xe_drm.h
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@ -350,15 +350,16 @@ struct drm_xe_query_gt {
__u32 clock_freq;
/**
* @near_mem_regions: Bit mask of instances from
* drm_xe_query_mem_regions that is near the current engines of this GT.
* drm_xe_query_mem_regions that are nearest to the current engines
* of this GT.
*/
__u64 near_mem_regions;
/**
* @far_mem_regions: Bit mask of instances from
* drm_xe_query_mem_regions that is far from the engines of this GT.
* In general, it has extra indirections when compared to the
* drm_xe_query_mem_regions that are far from the engines of this GT.
* In general, they have extra indirections when compared to the
* @near_mem_regions. For a discrete device this could mean system
* memory and memory living in a different Tile.
* memory and memory living in a different tile.
*/
__u64 far_mem_regions;
/** @reserved: Reserved */
@ -540,8 +541,25 @@ struct drm_xe_gem_create {
*/
__u32 handle;
/**
* @cpu_caching: The CPU caching mode to select for this object. If
* mmaping the object the mode selected here will also be used.
*
* Supported values:
*
* DRM_XE_GEM_CPU_CACHING_WB: Allocate the pages with write-back
* caching. On iGPU this can't be used for scanout surfaces. Currently
* not allowed for objects placed in VRAM.
*
* DRM_XE_GEM_CPU_CACHING_WC: Allocate the pages as write-combined. This
* is uncached. Scanout surfaces should likely use this. All objects
* that can be placed in VRAM must use this.
*/
#define DRM_XE_GEM_CPU_CACHING_WB 1
#define DRM_XE_GEM_CPU_CACHING_WC 2
__u16 cpu_caching;
/** @pad: MBZ */
__u32 pad;
__u16 pad;
/** @reserved: Reserved */
__u64 reserved[2];
@ -618,8 +636,48 @@ struct drm_xe_vm_bind_op {
*/
__u32 obj;
/**
* @pat_index: The platform defined @pat_index to use for this mapping.
* The index basically maps to some predefined memory attributes,
* including things like caching, coherency, compression etc. The exact
* meaning of the pat_index is platform specific and defined in the
* Bspec and PRMs. When the KMD sets up the binding the index here is
* encoded into the ppGTT PTE.
*
* For coherency the @pat_index needs to be at least 1way coherent when
* drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD
* will extract the coherency mode from the @pat_index and reject if
* there is a mismatch (see note below for pre-MTL platforms).
*
* Note: On pre-MTL platforms there is only a caching mode and no
* explicit coherency mode, but on such hardware there is always a
* shared-LLC (or is dgpu) so all GT memory accesses are coherent with
* CPU caches even with the caching mode set as uncached. It's only the
* display engine that is incoherent (on dgpu it must be in VRAM which
* is always mapped as WC on the CPU). However to keep the uapi somewhat
* consistent with newer platforms the KMD groups the different cache
* levels into the following coherency buckets on all pre-MTL platforms:
*
* ppGTT UC -> COH_NONE
* ppGTT WC -> COH_NONE
* ppGTT WT -> COH_NONE
* ppGTT WB -> COH_AT_LEAST_1WAY
*
* In practice UC/WC/WT should only ever used for scanout surfaces on
* such platforms (or perhaps in general for dma-buf if shared with
* another device) since it is only the display engine that is actually
* incoherent. Everything else should typically use WB given that we
* have a shared-LLC. On MTL+ this completely changes and the HW
* defines the coherency mode as part of the @pat_index, where
* incoherent GT access is possible.
*
* Note: For userptr and externally imported dma-buf the kernel expects
* either 1WAY or 2WAY for the @pat_index.
*/
__u16 pat_index;
/** @pad: MBZ */
__u32 pad;
__u16 pad;
union {
/**