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include: update drm-uapi
`drm.h` was missing a `#include <stdint.h>`, which was completely breaking the non-linux builds after272f9cfe6a("dri: Use DRM_FORMAT_* instead of defining our own copy.") started making use of it. Fixes:272f9cfe6a("dri: Use DRM_FORMAT_* instead of defining our own copy.") Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/950 Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Eric Engestrom
parent
3b8aeb0906
commit
02b3aa3cf3
@ -13,9 +13,8 @@ $ make headers_install INSTALL_HDR_PATH=/path/to/install
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The last update was done at the following kernel commit :
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commit a5f2fafece141ef3509e686cea576366d55cabb6
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Merge: 71f4e45a4ed3 860433ed2a55
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Author: Dave Airlie <airlied@redhat.com>
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Date: Wed Feb 20 12:16:30 2019 +1000
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commit 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c
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Author: Linus Torvalds <torvalds@linux-foundation.org>
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Date: Mon Sep 30 10:35:40 2019 -0700
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Merge https://gitlab.freedesktop.org/drm/msm into drm-next
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Linux 5.4-rc1
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@ -44,6 +44,7 @@ typedef unsigned int drm_handle_t;
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#else /* One of the BSDs */
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#include <stdint.h>
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#include <sys/ioccom.h>
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#include <sys/types.h>
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typedef int8_t __s8;
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@ -643,6 +644,7 @@ struct drm_gem_open {
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#define DRM_CAP_PAGE_FLIP_TARGET 0x11
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#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
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#define DRM_CAP_SYNCOBJ 0x13
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#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
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/** DRM_IOCTL_GET_CAP ioctl argument type */
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struct drm_get_cap {
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@ -729,8 +731,18 @@ struct drm_syncobj_handle {
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__u32 pad;
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};
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struct drm_syncobj_transfer {
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__u32 src_handle;
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__u32 dst_handle;
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__u64 src_point;
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__u64 dst_point;
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__u32 flags;
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__u32 pad;
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};
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
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struct drm_syncobj_wait {
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__u64 handles;
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/* absolute timeout */
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@ -741,12 +753,33 @@ struct drm_syncobj_wait {
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__u32 pad;
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};
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struct drm_syncobj_timeline_wait {
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__u64 handles;
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/* wait on specific timeline point for every handles*/
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__u64 points;
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/* absolute timeout */
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__s64 timeout_nsec;
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__u32 count_handles;
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__u32 flags;
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__u32 first_signaled; /* only valid when not waiting all */
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__u32 pad;
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};
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struct drm_syncobj_array {
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__u64 handles;
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__u32 count_handles;
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__u32 pad;
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};
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struct drm_syncobj_timeline_array {
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__u64 handles;
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__u64 points;
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__u32 count_handles;
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__u32 pad;
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};
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/* Query current scanout sequence number */
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struct drm_crtc_get_sequence {
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__u32 crtc_id; /* requested crtc_id */
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@ -903,6 +936,11 @@ extern "C" {
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#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
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#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
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#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
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#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
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#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
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#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
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/**
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* Device specific ioctls should only be in their respective headers
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* The device specific ioctl range is from 0x40 to 0x9f.
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@ -33,7 +33,15 @@
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extern "C" {
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#endif
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#define DRM_DISPLAY_INFO_LEN 32
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/**
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* DOC: overview
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*
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* DRM exposes many UAPI and structure definition to have a consistent
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* and standardized interface with user.
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* Userspace can refer to these structure definitions and UAPI formats
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* to communicate to driver
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*/
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#define DRM_CONNECTOR_NAME_LEN 32
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#define DRM_DISPLAY_MODE_LEN 32
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#define DRM_PROP_NAME_LEN 32
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@ -353,6 +361,7 @@ enum drm_mode_subconnector {
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#define DRM_MODE_CONNECTOR_DSI 16
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#define DRM_MODE_CONNECTOR_DPI 17
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#define DRM_MODE_CONNECTOR_WRITEBACK 18
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#define DRM_MODE_CONNECTOR_SPI 19
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struct drm_mode_get_connector {
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@ -622,7 +631,8 @@ struct drm_color_ctm {
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struct drm_color_lut {
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/*
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* Data is U0.16 fixed point format.
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* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
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* 0xffff == 1.0.
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*/
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__u16 red;
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__u16 green;
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@ -630,6 +640,92 @@ struct drm_color_lut {
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__u16 reserved;
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};
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/**
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* struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.
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*
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* HDR Metadata Infoframe as per CTA 861.G spec. This is expected
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* to match exactly with the spec.
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*
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* Userspace is expected to pass the metadata information as per
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* the format described in this structure.
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*/
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struct hdr_metadata_infoframe {
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/**
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* @eotf: Electro-Optical Transfer Function (EOTF)
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* used in the stream.
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*/
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__u8 eotf;
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/**
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* @metadata_type: Static_Metadata_Descriptor_ID.
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*/
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__u8 metadata_type;
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/**
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* @display_primaries: Color Primaries of the Data.
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* These are coded as unsigned 16-bit values in units of
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* 0.00002, where 0x0000 represents zero and 0xC350
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* represents 1.0000.
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* @display_primaries.x: X cordinate of color primary.
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* @display_primaries.y: Y cordinate of color primary.
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*/
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struct {
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__u16 x, y;
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} display_primaries[3];
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/**
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* @white_point: White Point of Colorspace Data.
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* These are coded as unsigned 16-bit values in units of
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* 0.00002, where 0x0000 represents zero and 0xC350
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* represents 1.0000.
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* @white_point.x: X cordinate of whitepoint of color primary.
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* @white_point.y: Y cordinate of whitepoint of color primary.
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*/
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struct {
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__u16 x, y;
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} white_point;
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/**
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* @max_display_mastering_luminance: Max Mastering Display Luminance.
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* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
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* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
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*/
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__u16 max_display_mastering_luminance;
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/**
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* @min_display_mastering_luminance: Min Mastering Display Luminance.
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* This value is coded as an unsigned 16-bit value in units of
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* 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
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* represents 6.5535 cd/m2.
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*/
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__u16 min_display_mastering_luminance;
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/**
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* @max_cll: Max Content Light Level.
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* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
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* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
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*/
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__u16 max_cll;
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/**
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* @max_fall: Max Frame Average Light Level.
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* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
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* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
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*/
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__u16 max_fall;
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};
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/**
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* struct hdr_output_metadata - HDR output metadata
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*
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* Metadata Information to be passed from userspace
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*/
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struct hdr_output_metadata {
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/**
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* @metadata_type: Static_Metadata_Descriptor_ID.
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*/
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__u32 metadata_type;
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/**
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* @hdmi_metadata_type1: HDR Metadata Infoframe.
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*/
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union {
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struct hdr_metadata_infoframe hdmi_metadata_type1;
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};
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};
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#define DRM_MODE_PAGE_FLIP_EVENT 0x01
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#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
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#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
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@ -803,6 +899,10 @@ struct drm_format_modifier {
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};
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/**
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* struct drm_mode_create_blob - Create New block property
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* @data: Pointer to data to copy.
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* @length: Length of data to copy.
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* @blob_id: new property ID.
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* Create a new 'blob' data property, copying length bytes from data pointer,
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* and returning new blob ID.
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*/
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@ -816,6 +916,8 @@ struct drm_mode_create_blob {
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};
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/**
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* struct drm_mode_destroy_blob - Destroy user blob
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* @blob_id: blob_id to destroy
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* Destroy a user-created blob property.
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*/
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struct drm_mode_destroy_blob {
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@ -823,6 +925,12 @@ struct drm_mode_destroy_blob {
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};
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/**
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* struct drm_mode_create_lease - Create lease
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* @object_ids: Pointer to array of object ids.
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* @object_count: Number of object ids.
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* @flags: flags for new FD.
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* @lessee_id: unique identifier for lessee.
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* @fd: file descriptor to new drm_master file.
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* Lease mode resources, creating another drm_master.
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*/
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struct drm_mode_create_lease {
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@ -840,6 +948,10 @@ struct drm_mode_create_lease {
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};
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/**
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* struct drm_mode_list_lessees - List lessees
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* @count_lessees: Number of lessees.
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* @pad: pad.
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* @lessees_ptr: Pointer to lessess.
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* List lesses from a drm_master
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*/
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struct drm_mode_list_lessees {
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@ -860,6 +972,10 @@ struct drm_mode_list_lessees {
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};
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/**
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* struct drm_mode_get_lease - Get Lease
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* @count_objects: Number of leased objects.
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* @pad: pad.
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* @objects_ptr: Pointer to objects.
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* Get leased objects
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*/
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struct drm_mode_get_lease {
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@ -880,6 +996,8 @@ struct drm_mode_get_lease {
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};
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/**
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* struct drm_mode_revoke_lease - Revoke lease
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* @lessee_id: Unique ID of lessee.
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* Revoke lease
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*/
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struct drm_mode_revoke_lease {
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@ -73,6 +73,7 @@ struct drm_etnaviv_timespec {
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#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
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#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
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#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
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#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
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#define ETNA_MAX_PIPES 4
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@ -148,6 +149,11 @@ struct drm_etnaviv_gem_submit_reloc {
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* then patching the cmdstream for this entry is skipped. This can
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* avoid kernel needing to map/access the cmdstream bo in the common
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* case.
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* If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
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* field is interpreted as the fixed location to map the bo into the gpu
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* virtual address space. If the kernel is unable to map the buffer at
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* this location the submit will fail. This means userspace is responsible
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* for the whole gpu virtual address management.
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*/
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#define ETNA_SUBMIT_BO_READ 0x0001
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#define ETNA_SUBMIT_BO_WRITE 0x0002
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@ -177,9 +183,11 @@ struct drm_etnaviv_gem_submit_pmr {
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#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
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#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
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#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
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#define ETNA_SUBMIT_SOFTPIN 0x0008
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#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
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ETNA_SUBMIT_FENCE_FD_IN | \
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ETNA_SUBMIT_FENCE_FD_OUT)
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ETNA_SUBMIT_FENCE_FD_OUT| \
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ETNA_SUBMIT_SOFTPIN)
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#define ETNA_PIPE_3D 0x00
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#define ETNA_PIPE_2D 0x01
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#define ETNA_PIPE_VG 0x02
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@ -62,6 +62,28 @@ extern "C" {
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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/*
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* i915_user_extension: Base class for defining a chain of extensions
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*
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* Many interfaces need to grow over time. In most cases we can simply
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* extend the struct and have userspace pass in more data. Another option,
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* as demonstrated by Vulkan's approach to providing extensions for forward
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* and backward compatibility, is to use a list of optional structs to
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* provide those extra details.
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*
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* The key advantage to using an extension chain is that it allows us to
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* redefine the interface more easily than an ever growing struct of
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* increasing complexity, and for large parts of that interface to be
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* entirely optional. The downside is more pointer chasing; chasing across
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* the boundary with pointers encapsulated inside u64.
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*/
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struct i915_user_extension {
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__u64 next_extension;
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__u32 name;
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__u32 flags; /* All undefined bits must be zero. */
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__u32 rsvd[4]; /* Reserved for future use; must be zero. */
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};
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/*
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* MOCS indexes used for GPU surfaces, defining the cacheability of the
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* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
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@ -99,9 +121,25 @@ enum drm_i915_gem_engine_class {
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I915_ENGINE_CLASS_VIDEO = 2,
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I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
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/* should be kept compact */
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I915_ENGINE_CLASS_INVALID = -1
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};
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/*
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* There may be more than one engine fulfilling any role within the system.
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* Each engine of a class is given a unique instance number and therefore
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* any engine can be specified by its class:instance tuplet. APIs that allow
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* access to any engine in the system will use struct i915_engine_class_instance
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* for this identification.
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*/
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struct i915_engine_class_instance {
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__u16 engine_class; /* see enum drm_i915_gem_engine_class */
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__u16 engine_instance;
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#define I915_ENGINE_CLASS_INVALID_NONE -1
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#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
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};
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/**
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* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
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*
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@ -319,6 +357,9 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_PERF_ADD_CONFIG 0x37
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#define DRM_I915_PERF_REMOVE_CONFIG 0x38
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#define DRM_I915_QUERY 0x39
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#define DRM_I915_GEM_VM_CREATE 0x3a
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#define DRM_I915_GEM_VM_DESTROY 0x3b
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/* Must be kept compact -- no holes */
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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@ -367,6 +408,7 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
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#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
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#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
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@ -377,6 +419,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
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#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
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#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
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#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
|
||||
#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
|
||||
|
||||
/* Allow drivers to submit batchbuffers directly to hardware, relying
|
||||
* on the security mechanisms provided by hardware.
|
||||
@ -476,6 +520,8 @@ typedef struct drm_i915_irq_wait {
|
||||
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
|
||||
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
|
||||
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
|
||||
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
|
||||
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
|
||||
|
||||
#define I915_PARAM_HUC_STATUS 42
|
||||
|
||||
@ -559,6 +605,14 @@ typedef struct drm_i915_irq_wait {
|
||||
*/
|
||||
#define I915_PARAM_MMAP_GTT_COHERENT 52
|
||||
|
||||
/*
|
||||
* Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
|
||||
* execution through use of explicit fence support.
|
||||
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
|
||||
*/
|
||||
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
__s32 param;
|
||||
/*
|
||||
@ -574,6 +628,7 @@ typedef struct drm_i915_getparam {
|
||||
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
|
||||
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
|
||||
#define I915_SETPARAM_NUM_USED_FENCES 4
|
||||
/* Must be kept compact -- no holes */
|
||||
|
||||
typedef struct drm_i915_setparam {
|
||||
int param;
|
||||
@ -972,7 +1027,7 @@ struct drm_i915_gem_execbuffer2 {
|
||||
* struct drm_i915_gem_exec_fence *fences.
|
||||
*/
|
||||
__u64 cliprects_ptr;
|
||||
#define I915_EXEC_RING_MASK (7<<0)
|
||||
#define I915_EXEC_RING_MASK (0x3f)
|
||||
#define I915_EXEC_DEFAULT (0<<0)
|
||||
#define I915_EXEC_RENDER (1<<0)
|
||||
#define I915_EXEC_BSD (2<<0)
|
||||
@ -1078,7 +1133,16 @@ struct drm_i915_gem_execbuffer2 {
|
||||
*/
|
||||
#define I915_EXEC_FENCE_ARRAY (1<<19)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
|
||||
/*
|
||||
* Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
|
||||
* a sync_file fd to wait upon (in a nonblocking manner) prior to executing
|
||||
* the batch.
|
||||
*
|
||||
* Returns -EINVAL if the sync_file fd cannot be found.
|
||||
*/
|
||||
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
@ -1120,32 +1184,34 @@ struct drm_i915_gem_busy {
|
||||
* as busy may become idle before the ioctl is completed.
|
||||
*
|
||||
* Furthermore, if the object is busy, which engine is busy is only
|
||||
* provided as a guide. There are race conditions which prevent the
|
||||
* report of which engines are busy from being always accurate.
|
||||
* However, the converse is not true. If the object is idle, the
|
||||
* result of the ioctl, that all engines are idle, is accurate.
|
||||
* provided as a guide and only indirectly by reporting its class
|
||||
* (there may be more than one engine in each class). There are race
|
||||
* conditions which prevent the report of which engines are busy from
|
||||
* being always accurate. However, the converse is not true. If the
|
||||
* object is idle, the result of the ioctl, that all engines are idle,
|
||||
* is accurate.
|
||||
*
|
||||
* The returned dword is split into two fields to indicate both
|
||||
* the engines on which the object is being read, and the
|
||||
* engine on which it is currently being written (if any).
|
||||
* the engine classess on which the object is being read, and the
|
||||
* engine class on which it is currently being written (if any).
|
||||
*
|
||||
* The low word (bits 0:15) indicate if the object is being written
|
||||
* to by any engine (there can only be one, as the GEM implicit
|
||||
* synchronisation rules force writes to be serialised). Only the
|
||||
* engine for the last write is reported.
|
||||
* engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
|
||||
* 1 not 0 etc) for the last write is reported.
|
||||
*
|
||||
* The high word (bits 16:31) are a bitmask of which engines are
|
||||
* currently reading from the object. Multiple engines may be
|
||||
* The high word (bits 16:31) are a bitmask of which engines classes
|
||||
* are currently reading from the object. Multiple engines may be
|
||||
* reading from the object simultaneously.
|
||||
*
|
||||
* The value of each engine is the same as specified in the
|
||||
* EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
|
||||
* Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
|
||||
* the I915_EXEC_RENDER engine for execution, and so it is never
|
||||
* The value of each engine class is the same as specified in the
|
||||
* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
|
||||
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
|
||||
* reported as active itself. Some hardware may have parallel
|
||||
* execution engines, e.g. multiple media engines, which are
|
||||
* mapped to the same identifier in the EXECBUFFER2 ioctl and
|
||||
* so are not separately reported for busyness.
|
||||
* mapped to the same class identifier and so are not separately
|
||||
* reported for busyness.
|
||||
*
|
||||
* Caveat emptor:
|
||||
* Only the boolean result of this query is reliable; that is whether
|
||||
@ -1412,65 +1478,18 @@ struct drm_i915_gem_wait {
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create {
|
||||
/* output: id of new context*/
|
||||
__u32 ctx_id;
|
||||
__u32 ctx_id; /* output: id of new context*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_destroy {
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_reg_read {
|
||||
/*
|
||||
* Register offset.
|
||||
* For 64bit wide registers where the upper 32bits don't immediately
|
||||
* follow the lower 32bits, the offset of the lower 32bits must
|
||||
* be specified
|
||||
*/
|
||||
__u64 offset;
|
||||
#define I915_REG_READ_8B_WA (1ul << 0)
|
||||
|
||||
__u64 val; /* Return value */
|
||||
};
|
||||
/* Known registers:
|
||||
*
|
||||
* Render engine timestamp - 0x2358 + 64bit - gen7+
|
||||
* - Note this register returns an invalid value if using the default
|
||||
* single instruction 8byte read, in order to workaround that pass
|
||||
* flag I915_REG_READ_8B_WA in offset field.
|
||||
*
|
||||
*/
|
||||
|
||||
struct drm_i915_reset_stats {
|
||||
__u32 ctx_id;
|
||||
struct drm_i915_gem_context_create_ext {
|
||||
__u32 ctx_id; /* output: id of new context*/
|
||||
__u32 flags;
|
||||
|
||||
/* All resets since boot/module reload, for all contexts */
|
||||
__u32 reset_count;
|
||||
|
||||
/* Number of batches lost when active in GPU, for this context */
|
||||
__u32 batch_active;
|
||||
|
||||
/* Number of batches lost pending for execution, for this context */
|
||||
__u32 batch_pending;
|
||||
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_userptr {
|
||||
__u64 user_ptr;
|
||||
__u64 user_size;
|
||||
__u32 flags;
|
||||
#define I915_USERPTR_READ_ONLY 0x1
|
||||
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
|
||||
/**
|
||||
* Returned handle for the object.
|
||||
*
|
||||
* Object handles are nonzero.
|
||||
*/
|
||||
__u32 handle;
|
||||
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
|
||||
#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
|
||||
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
|
||||
(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
|
||||
__u64 extensions;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_param {
|
||||
@ -1511,6 +1530,43 @@ struct drm_i915_gem_context_param {
|
||||
* On creation, all new contexts are marked as recoverable.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
|
||||
|
||||
/*
|
||||
* The id of the associated virtual memory address space (ppGTT) of
|
||||
* this context. Can be retrieved and passed to another context
|
||||
* (on the same fd) for both to use the same ppGTT and so share
|
||||
* address layouts, and avoid reloading the page tables on context
|
||||
* switches between themselves.
|
||||
*
|
||||
* See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_VM 0x9
|
||||
|
||||
/*
|
||||
* I915_CONTEXT_PARAM_ENGINES:
|
||||
*
|
||||
* Bind this context to operate on this subset of available engines. Henceforth,
|
||||
* the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
|
||||
* an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
|
||||
* and upwards. Slots 0...N are filled in using the specified (class, instance).
|
||||
* Use
|
||||
* engine_class: I915_ENGINE_CLASS_INVALID,
|
||||
* engine_instance: I915_ENGINE_CLASS_INVALID_NONE
|
||||
* to specify a gap in the array that can be filled in later, e.g. by a
|
||||
* virtual engine used for load balancing.
|
||||
*
|
||||
* Setting the number of engines bound to the context to 0, by passing a zero
|
||||
* sized argument, will revert back to default settings.
|
||||
*
|
||||
* See struct i915_context_param_engines.
|
||||
*
|
||||
* Extensions:
|
||||
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
|
||||
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_ENGINES 0xa
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
@ -1539,13 +1595,13 @@ struct drm_i915_gem_context_param_sseu {
|
||||
/*
|
||||
* Engine class & instance to be configured or queried.
|
||||
*/
|
||||
__u16 engine_class;
|
||||
__u16 engine_instance;
|
||||
struct i915_engine_class_instance engine;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
* Unknown flags must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
|
||||
|
||||
/*
|
||||
* Mask of slices to enable for the context. Valid values are a subset
|
||||
@ -1573,6 +1629,199 @@ struct drm_i915_gem_context_param_sseu {
|
||||
__u32 rsvd;
|
||||
};
|
||||
|
||||
/*
|
||||
* i915_context_engines_load_balance:
|
||||
*
|
||||
* Enable load balancing across this set of engines.
|
||||
*
|
||||
* Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
|
||||
* used will proxy the execbuffer request onto one of the set of engines
|
||||
* in such a way as to distribute the load evenly across the set.
|
||||
*
|
||||
* The set of engines must be compatible (e.g. the same HW class) as they
|
||||
* will share the same logical GPU context and ring.
|
||||
*
|
||||
* To intermix rendering with the virtual engine and direct rendering onto
|
||||
* the backing engines (bypassing the load balancing proxy), the context must
|
||||
* be defined to use a single timeline for all engines.
|
||||
*/
|
||||
struct i915_context_engines_load_balance {
|
||||
struct i915_user_extension base;
|
||||
|
||||
__u16 engine_index;
|
||||
__u16 num_siblings;
|
||||
__u32 flags; /* all undefined flags must be zero */
|
||||
|
||||
__u64 mbz64; /* reserved for future use; must be zero */
|
||||
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
|
||||
struct i915_user_extension base; \
|
||||
__u16 engine_index; \
|
||||
__u16 num_siblings; \
|
||||
__u32 flags; \
|
||||
__u64 mbz64; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
/*
|
||||
* i915_context_engines_bond:
|
||||
*
|
||||
* Constructed bonded pairs for execution within a virtual engine.
|
||||
*
|
||||
* All engines are equal, but some are more equal than others. Given
|
||||
* the distribution of resources in the HW, it may be preferable to run
|
||||
* a request on a given subset of engines in parallel to a request on a
|
||||
* specific engine. We enable this selection of engines within a virtual
|
||||
* engine by specifying bonding pairs, for any given master engine we will
|
||||
* only execute on one of the corresponding siblings within the virtual engine.
|
||||
*
|
||||
* To execute a request in parallel on the master engine and a sibling requires
|
||||
* coordination with a I915_EXEC_FENCE_SUBMIT.
|
||||
*/
|
||||
struct i915_context_engines_bond {
|
||||
struct i915_user_extension base;
|
||||
|
||||
struct i915_engine_class_instance master;
|
||||
|
||||
__u16 virtual_index; /* index of virtual engine in ctx->engines[] */
|
||||
__u16 num_bonds;
|
||||
|
||||
__u64 flags; /* all undefined flags must be zero */
|
||||
__u64 mbz64[4]; /* reserved for future use; must be zero */
|
||||
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
|
||||
struct i915_user_extension base; \
|
||||
struct i915_engine_class_instance master; \
|
||||
__u16 virtual_index; \
|
||||
__u16 num_bonds; \
|
||||
__u64 flags; \
|
||||
__u64 mbz64[4]; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
struct i915_context_param_engines {
|
||||
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
|
||||
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
|
||||
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
|
||||
struct i915_engine_class_instance engines[0];
|
||||
} __attribute__((packed));
|
||||
|
||||
#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
|
||||
__u64 extensions; \
|
||||
struct i915_engine_class_instance engines[N__]; \
|
||||
} __attribute__((packed)) name__
|
||||
|
||||
struct drm_i915_gem_context_create_ext_setparam {
|
||||
#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
|
||||
struct i915_user_extension base;
|
||||
struct drm_i915_gem_context_param param;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create_ext_clone {
|
||||
#define I915_CONTEXT_CREATE_EXT_CLONE 1
|
||||
struct i915_user_extension base;
|
||||
__u32 clone_id;
|
||||
__u32 flags;
|
||||
#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
|
||||
#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
|
||||
#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
|
||||
#define I915_CONTEXT_CLONE_SSEU (1u << 3)
|
||||
#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
|
||||
#define I915_CONTEXT_CLONE_VM (1u << 5)
|
||||
#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
|
||||
__u64 rsvd;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_destroy {
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/*
|
||||
* DRM_I915_GEM_VM_CREATE -
|
||||
*
|
||||
* Create a new virtual memory address space (ppGTT) for use within a context
|
||||
* on the same file. Extensions can be provided to configure exactly how the
|
||||
* address space is setup upon creation.
|
||||
*
|
||||
* The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
|
||||
* returned in the outparam @id.
|
||||
*
|
||||
* No flags are defined, with all bits reserved and must be zero.
|
||||
*
|
||||
* An extension chain maybe provided, starting with @extensions, and terminated
|
||||
* by the @next_extension being 0. Currently, no extensions are defined.
|
||||
*
|
||||
* DRM_I915_GEM_VM_DESTROY -
|
||||
*
|
||||
* Destroys a previously created VM id, specified in @id.
|
||||
*
|
||||
* No extensions or flags are allowed currently, and so must be zero.
|
||||
*/
|
||||
struct drm_i915_gem_vm_control {
|
||||
__u64 extensions;
|
||||
__u32 flags;
|
||||
__u32 vm_id;
|
||||
};
|
||||
|
||||
struct drm_i915_reg_read {
|
||||
/*
|
||||
* Register offset.
|
||||
* For 64bit wide registers where the upper 32bits don't immediately
|
||||
* follow the lower 32bits, the offset of the lower 32bits must
|
||||
* be specified
|
||||
*/
|
||||
__u64 offset;
|
||||
#define I915_REG_READ_8B_WA (1ul << 0)
|
||||
|
||||
__u64 val; /* Return value */
|
||||
};
|
||||
|
||||
/* Known registers:
|
||||
*
|
||||
* Render engine timestamp - 0x2358 + 64bit - gen7+
|
||||
* - Note this register returns an invalid value if using the default
|
||||
* single instruction 8byte read, in order to workaround that pass
|
||||
* flag I915_REG_READ_8B_WA in offset field.
|
||||
*
|
||||
*/
|
||||
|
||||
struct drm_i915_reset_stats {
|
||||
__u32 ctx_id;
|
||||
__u32 flags;
|
||||
|
||||
/* All resets since boot/module reload, for all contexts */
|
||||
__u32 reset_count;
|
||||
|
||||
/* Number of batches lost when active in GPU, for this context */
|
||||
__u32 batch_active;
|
||||
|
||||
/* Number of batches lost pending for execution, for this context */
|
||||
__u32 batch_pending;
|
||||
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_userptr {
|
||||
__u64 user_ptr;
|
||||
__u64 user_size;
|
||||
__u32 flags;
|
||||
#define I915_USERPTR_READ_ONLY 0x1
|
||||
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
|
||||
/**
|
||||
* Returned handle for the object.
|
||||
*
|
||||
* Object handles are nonzero.
|
||||
*/
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
enum drm_i915_oa_format {
|
||||
I915_OA_FORMAT_A13 = 1, /* HSW only */
|
||||
I915_OA_FORMAT_A29, /* HSW only */
|
||||
@ -1734,6 +1983,8 @@ struct drm_i915_perf_oa_config {
|
||||
struct drm_i915_query_item {
|
||||
__u64 query_id;
|
||||
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
|
||||
#define DRM_I915_QUERY_ENGINE_INFO 2
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
/*
|
||||
* When set to zero by userspace, this is filled with the size of the
|
||||
@ -1831,6 +2082,47 @@ struct drm_i915_query_topology_info {
|
||||
__u8 data[];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_i915_engine_info
|
||||
*
|
||||
* Describes one engine and it's capabilities as known to the driver.
|
||||
*/
|
||||
struct drm_i915_engine_info {
|
||||
/** Engine class and instance. */
|
||||
struct i915_engine_class_instance engine;
|
||||
|
||||
/** Reserved field. */
|
||||
__u32 rsvd0;
|
||||
|
||||
/** Engine flags. */
|
||||
__u64 flags;
|
||||
|
||||
/** Capabilities of this engine. */
|
||||
__u64 capabilities;
|
||||
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
|
||||
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
|
||||
|
||||
/** Reserved fields. */
|
||||
__u64 rsvd1[4];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_i915_query_engine_info
|
||||
*
|
||||
* Engine info query enumerates all engines known to the driver by filling in
|
||||
* an array of struct drm_i915_engine_info structures.
|
||||
*/
|
||||
struct drm_i915_query_engine_info {
|
||||
/** Number of struct drm_i915_engine_info structs following. */
|
||||
__u32 num_engines;
|
||||
|
||||
/** MBZ */
|
||||
__u32 rsvd[3];
|
||||
|
||||
/** Marker for drm_i915_engine_info structures. */
|
||||
struct drm_i915_engine_info engines[];
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -37,6 +37,7 @@ extern "C" {
|
||||
#define DRM_V3D_GET_PARAM 0x04
|
||||
#define DRM_V3D_GET_BO_OFFSET 0x05
|
||||
#define DRM_V3D_SUBMIT_TFU 0x06
|
||||
#define DRM_V3D_SUBMIT_CSD 0x07
|
||||
|
||||
#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
|
||||
#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
|
||||
@ -45,6 +46,7 @@ extern "C" {
|
||||
#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
|
||||
#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
|
||||
#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
|
||||
#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
|
||||
|
||||
/**
|
||||
* struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
|
||||
@ -190,6 +192,7 @@ enum drm_v3d_param {
|
||||
DRM_V3D_PARAM_V3D_CORE0_IDENT1,
|
||||
DRM_V3D_PARAM_V3D_CORE0_IDENT2,
|
||||
DRM_V3D_PARAM_SUPPORTS_TFU,
|
||||
DRM_V3D_PARAM_SUPPORTS_CSD,
|
||||
};
|
||||
|
||||
struct drm_v3d_get_param {
|
||||
@ -230,6 +233,31 @@ struct drm_v3d_submit_tfu {
|
||||
__u32 out_sync;
|
||||
};
|
||||
|
||||
/* Submits a compute shader for dispatch. This job will block on any
|
||||
* previous compute shaders submitted on this fd, and any other
|
||||
* synchronization must be performed with in_sync/out_sync.
|
||||
*/
|
||||
struct drm_v3d_submit_csd {
|
||||
__u32 cfg[7];
|
||||
__u32 coef[4];
|
||||
|
||||
/* Pointer to a u32 array of the BOs that are referenced by the job.
|
||||
*/
|
||||
__u64 bo_handles;
|
||||
|
||||
/* Number of BO handles passed in (size is that times 4). */
|
||||
__u32 bo_handle_count;
|
||||
|
||||
/* sync object to block on before running the CSD job. Each
|
||||
* CSD job will execute in the order submitted to its FD.
|
||||
* Synchronization against rendering/TFU jobs or CSD from
|
||||
* other fds requires using sync objects.
|
||||
*/
|
||||
__u32 in_sync;
|
||||
/* Sync object to signal when the CSD job is done. */
|
||||
__u32 out_sync;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user