mirrors/mesa
0
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2024-11-23 18:24:13 +08:00
Code Issues Packages Projects Releases Wiki Activity

radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue

Browse Source 
The VA needs to be adjusted, otherwise the hw always writes at offset 0.

This fixes dEQP-VK.query_pool.statistics_query.*_cq.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25406>
(cherry picked from commit a9945216ba)
This commit is contained in:
Samuel Pitoiset 2023-09-26 18:19:59 +02:00 committed by Eric Engestrom
parent aa3f6b7926
commit 016a34ded5
2 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.pick_status.json
View File

@ -121,7 +121,7 @@
"description": "radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

12
src/amd/vulkan/radv_query.c
View File

@ -1795,6 +1795,12 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
}
if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
uint32_t cs_invoc_offset =
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
va += cs_invoc_offset;
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
radeon_emit(cs, va);
@ -1935,6 +1941,12 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool,
}
va += pipelinestat_block_size;
if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
uint32_t cs_invoc_offset =
radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
va += cs_invoc_offset;
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
radeon_emit(cs, va);