diff --git a/.pick_status.json b/.pick_status.json
index e655ab76aa4..99e63949709 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -121,7 +121,7 @@
         "description": "radv: fix COMPUTE_SHADER_INVOCATIONS query on compute queue",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 0ddac8bd72c..dde945757ff 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1795,6 +1795,12 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo
          cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_START_PIPELINE_STATS;
       }
 
+      if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
+         uint32_t cs_invoc_offset =
+            radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
+         va += cs_invoc_offset;
+      }
+
       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
       radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
       radeon_emit(cs, va);
@@ -1935,6 +1941,12 @@ emit_end_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *pool,
       }
       va += pipelinestat_block_size;
 
+      if (cmd_buffer->qf == RADV_QUEUE_COMPUTE) {
+         uint32_t cs_invoc_offset =
+            radv_get_pipelinestat_query_offset(VK_QUERY_PIPELINE_STATISTIC_COMPUTE_SHADER_INVOCATIONS_BIT);
+         va += cs_invoc_offset;
+      }
+
       radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
       radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
       radeon_emit(cs, va);