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[gve] Add driver for Google Virtual Ethernet NIC
The Google Virtual Ethernet NIC (GVE or gVNIC) is found only in Google Cloud instances. There is essentially zero documentation available beyond the mostly uncommented source code in the Linux kernel. Signed-off-by: Michael Brown <mcb30@ipxe.org>
This commit is contained in:
Michael Brown
parent
5a9f476d4f
commit
c7b76e3adc
@ -29,6 +29,9 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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/* Corrupt every N received PeerDist packets */
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#define PEERBLK_CORRUPT_RATE 0
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/* Experience virtual machine migration on every N watchdog checks */
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#define VM_MIGRATED_RATE 0
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#include <config/local/fault.h>
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#endif /* CONFIG_FAULT_H */
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1607
src/drivers/net/gve.c
Normal file
1607
src/drivers/net/gve.c
Normal file
File diff suppressed because it is too large
Load Diff
702
src/drivers/net/gve.h
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702
src/drivers/net/gve.h
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@ -0,0 +1,702 @@
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#ifndef _GVE_H
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#define _GVE_H
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/** @file
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*
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* Google Virtual Ethernet network driver
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*
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* The Google Virtual Ethernet NIC (GVE or gVNIC) is found only in
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* Google Cloud instances. There is essentially zero documentation
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* available beyond the mostly uncommented source code in the Linux
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* kernel.
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*/
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FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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#include <stdint.h>
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#include <ipxe/dma.h>
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#include <ipxe/pci.h>
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#include <ipxe/in.h>
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#include <ipxe/uaccess.h>
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#include <ipxe/process.h>
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#include <ipxe/retry.h>
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struct gve_nic;
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/**
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* A Google Cloud MAC address
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*
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* Google Cloud locally assigned MAC addresses encode the local IPv4
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* address in the trailing 32 bits, presumably as a performance
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* optimisation to allow ARP resolution to be skipped by a suitably
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* aware network stack.
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*/
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struct google_mac {
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/** Reserved */
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uint8_t reserved[2];
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/** Local IPv4 address */
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struct in_addr in;
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} __attribute__ (( packed ));
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/** Page size */
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#define GVE_PAGE_SIZE 0x1000
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/**
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* Address alignment
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*
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* All DMA data structure base addresses seem to need to be aligned to
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* a page boundary. (This is not documented anywhere, but is inferred
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* from existing source code and experimentation.)
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*/
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#define GVE_ALIGN GVE_PAGE_SIZE
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/**
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* Length alignment
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*
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* All DMA data structure lengths seem to need to be aligned to a
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* multiple of 64 bytes. (This is not documented anywhere, but is
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* inferred from existing source code and experimentation.)
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*/
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#define GVE_LEN_ALIGN 64
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/** Maximum number of pages per queue (must be a power of two) */
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#define GVE_QPL_MAX 16
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/** Configuration BAR */
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#define GVE_CFG_BAR PCI_BASE_ADDRESS_0
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/**
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* Configuration BAR size
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*
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* All registers within the configuration BAR are big-endian.
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*/
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#define GVE_CFG_SIZE 0x1000
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/** Device status */
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#define GVE_CFG_DEVSTAT 0x0000
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#define GVE_CFG_DEVSTAT_RESET 0x00000010UL /**< Device is reset */
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/** Driver status */
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#define GVE_CFG_DRVSTAT 0x0004
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#define GVE_CFG_DRVSTAT_RUN 0x00000001UL /**< Run admin queue */
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/** Maximum time to wait for reset */
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#define GVE_RESET_MAX_WAIT_MS 500
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/** Admin queue page frame number (for older devices) */
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#define GVE_CFG_ADMIN_PFN 0x0010
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/** Admin queue doorbell */
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#define GVE_CFG_ADMIN_DB 0x0014
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/** Admin queue event counter */
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#define GVE_CFG_ADMIN_EVT 0x0018
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/** Driver version (8-bit register) */
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#define GVE_CFG_VERSION 0x001f
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/** Admin queue base address high 32 bits */
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#define GVE_CFG_ADMIN_BASE_HI 0x0020
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/** Admin queue base address low 32 bits */
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#define GVE_CFG_ADMIN_BASE_LO 0x0024
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/** Admin queue base address length (16-bit register) */
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#define GVE_CFG_ADMIN_LEN 0x0028
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/** Doorbell BAR */
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#define GVE_DB_BAR PCI_BASE_ADDRESS_2
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/**
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* Admin queue entry header
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*
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* All values within admin queue entries are big-endian.
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*/
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struct gve_admin_header {
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/** Reserved */
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uint8_t reserved[3];
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/** Operation code */
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uint8_t opcode;
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/** Status */
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uint32_t status;
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} __attribute__ (( packed ));
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/** Command succeeded */
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#define GVE_ADMIN_STATUS_OK 0x00000001
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/** Simple admin command */
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struct gve_admin_simple {
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/** Header */
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struct gve_admin_header hdr;
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/** ID */
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uint32_t id;
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} __attribute__ (( packed ));
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/** Describe device command */
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#define GVE_ADMIN_DESCRIBE 0x0001
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/** Describe device command */
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struct gve_admin_describe {
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/** Header */
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struct gve_admin_header hdr;
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/** Descriptor buffer address */
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uint64_t addr;
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/** Descriptor version */
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uint32_t ver;
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/** Descriptor maximum length */
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uint32_t len;
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} __attribute__ (( packed ));
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/** Device descriptor version */
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#define GVE_ADMIN_DESCRIBE_VER 1
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/** Device descriptor */
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struct gve_device_descriptor {
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/** Reserved */
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uint8_t reserved_a[10];
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/** Number of transmit queue entries */
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uint16_t tx_count;
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/** Number of receive queue entries */
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uint16_t rx_count;
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/** Reserved */
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uint8_t reserved_b[2];
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/** Maximum transmit unit */
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uint16_t mtu;
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/** Number of event counters */
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uint16_t counters;
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/** Reserved */
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uint8_t reserved_c[4];
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/** MAC address */
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struct google_mac mac;
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/** Reserved */
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uint8_t reserved_d[10];
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} __attribute__ (( packed ));
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/** Configure device resources command */
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#define GVE_ADMIN_CONFIGURE 0x0002
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/** Configure device resources command */
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struct gve_admin_configure {
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/** Header */
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struct gve_admin_header hdr;
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/** Event counter array */
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uint64_t events;
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/** IRQ doorbell address */
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uint64_t irqs;
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/** Number of event counters */
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uint32_t num_events;
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/** Number of IRQ doorbells */
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uint32_t num_irqs;
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/** IRQ doorbell stride */
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uint32_t irq_stride;
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} __attribute__ (( packed ));
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/** Register page list command */
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#define GVE_ADMIN_REGISTER 0x0003
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/** Register page list command */
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struct gve_admin_register {
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/** Header */
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struct gve_admin_header hdr;
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/** Page list ID */
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uint32_t id;
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/** Number of pages */
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uint32_t count;
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/** Address list address */
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uint64_t addr;
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/** Page size */
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uint64_t size;
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} __attribute__ (( packed ));
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/** Page list */
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struct gve_pages {
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/** Page address */
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uint64_t addr[GVE_QPL_MAX];
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} __attribute__ (( packed ));
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/** Unregister page list command */
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#define GVE_ADMIN_UNREGISTER 0x0004
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/** Create transmit queue command */
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#define GVE_ADMIN_CREATE_TX 0x0005
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/** Create transmit queue command */
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struct gve_admin_create_tx {
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/** Header */
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struct gve_admin_header hdr;
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/** Queue ID */
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uint32_t id;
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/** Reserved */
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uint8_t reserved_a[4];
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/** Queue resources address */
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uint64_t res;
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/** Descriptor ring address */
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uint64_t desc;
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/** Queue page list ID */
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uint32_t qpl_id;
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/** Notification channel ID */
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uint32_t notify_id;
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} __attribute__ (( packed ));
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/** Create receive queue command */
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#define GVE_ADMIN_CREATE_RX 0x0006
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/** Create receive queue command */
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struct gve_admin_create_rx {
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/** Header */
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struct gve_admin_header hdr;
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/** Queue ID */
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uint32_t id;
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/** Index */
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uint32_t index;
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/** Reserved */
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uint8_t reserved_a[4];
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/** Notification channel ID */
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uint32_t notify_id;
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/** Queue resources address */
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uint64_t res;
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/** Completion ring address */
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uint64_t cmplt;
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/** Descriptor ring address */
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uint64_t desc;
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/** Queue page list ID */
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uint32_t qpl_id;
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/** Reserved */
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uint8_t reserved_b[2];
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/** Packet buffer size */
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uint16_t bufsz;
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} __attribute__ (( packed ));
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/** Destroy transmit queue command */
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#define GVE_ADMIN_DESTROY_TX 0x0007
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/** Destroy receive queue command */
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#define GVE_ADMIN_DESTROY_RX 0x0008
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/** Deconfigure device resources command */
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#define GVE_ADMIN_DECONFIGURE 0x0009
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/** An admin queue command */
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union gve_admin_command {
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/** Header */
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struct gve_admin_header hdr;
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/** Simple command */
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struct gve_admin_simple simple;
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/** Describe device */
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struct gve_admin_describe desc;
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/** Configure device resources */
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struct gve_admin_configure conf;
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/** Register page list */
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struct gve_admin_register reg;
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/** Create transmit queue */
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struct gve_admin_create_tx create_tx;
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/** Create receive queue */
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struct gve_admin_create_rx create_rx;
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/** Padding */
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uint8_t pad[64];
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};
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/**
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* Number of admin queue commands
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*
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* This is theoretically a policy decision. However, older revisions
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* of the hardware seem to have only the "admin queue page frame
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* number" register and no "admin queue length" register, with the
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* implication that the admin queue must be exactly one page in
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* length.
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*
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* Choose to use a one page (4kB) admin queue for both older and newer
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* versions of the hardware, to minimise variability.
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*/
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#define GVE_ADMIN_COUNT ( GVE_PAGE_SIZE / sizeof ( union gve_admin_command ) )
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/** Admin queue */
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struct gve_admin {
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/** Commands */
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union gve_admin_command *cmd;
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/** Producer counter */
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uint32_t prod;
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/** DMA mapping */
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struct dma_mapping map;
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};
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/** Scratch buffer for admin queue commands */
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struct gve_scratch {
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/** Buffer contents */
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union {
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/** Device descriptor */
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struct gve_device_descriptor desc;
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/** Page address list */
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struct gve_pages pages;
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} *buf;
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/** DMA mapping */
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struct dma_mapping map;
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};
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/**
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* An event counter
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*
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* Written by the device to indicate completions. The device chooses
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* which counter to use for each transmit queue, and stores the index
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* of the chosen counter in the queue resources.
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*/
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struct gve_event {
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/** Number of events that have occurred */
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volatile uint32_t count;
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} __attribute__ (( packed ));
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/**
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* Maximum number of event counters
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*
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* We tell the device how many event counters we have provided via the
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* "configure device resources" admin queue command. The device will
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* accept being given only a single counter, but will subsequently
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* fail to create a receive queue.
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*
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* There is, of course, no documentation indicating how may event
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* counters actually need to be provided. In the absence of evidence
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* to the contrary, assume that 16 counters (i.e. the smallest number
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* we can allocate, given the length alignment constraint on
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* allocations) will be sufficient.
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*/
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#define GVE_EVENT_MAX ( GVE_LEN_ALIGN / sizeof ( struct gve_event ) )
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/** Event counter array */
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struct gve_events {
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/** Event counters */
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struct gve_event *event;
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/** DMA mapping */
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struct dma_mapping map;
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/** Actual number of event counters */
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unsigned int count;
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};
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/** An interrupt channel */
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struct gve_irq {
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/** Interrupt doorbell index (within doorbell BAR) */
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uint32_t db_idx;
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/** Reserved */
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uint8_t reserved[60];
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} __attribute__ (( packed ));
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/**
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* Number of interrupt channels
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*
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* We tell the device how many interrupt channels we have provided via
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* the "configure device resources" admin queue command. The device
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* will accept being given zero interrupt channels, but will
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* subsequently fail to create more than a single queue (either
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* transmit or receive).
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*
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* There is, of course, no documentation indicating how may interrupt
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* channels actually need to be provided. In the absence of evidence
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* to the contrary, assume that two channels (one for transmit, one
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* for receive) will be sufficient.
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*/
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#define GVE_IRQ_COUNT 2
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/** Interrupt channel array */
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struct gve_irqs {
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/** Interrupt channels */
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struct gve_irq *irq;
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/** DMA mapping */
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struct dma_mapping map;
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/** Interrupt doorbells */
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volatile uint32_t *db[GVE_IRQ_COUNT];
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};
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/** Disable interrupts */
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#define GVE_IRQ_DISABLE 0x40000000UL
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/**
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* Queue resources
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*
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* Written by the device to indicate the indices of the chosen event
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* counter and descriptor doorbell register.
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*
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* This appears to be a largely pointless data structure: the relevant
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* information is static for the lifetime of the queue and could
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* trivially have been returned in the response for the "create
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* transmit/receive queue" command, instead of requiring yet another
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* page-aligned coherent DMA buffer allocation.
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*/
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struct gve_resources {
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/** Descriptor doorbell index (within doorbell BAR) */
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uint32_t db_idx;
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/** Event counter index (within event counter array) */
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uint32_t evt_idx;
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/** Reserved */
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uint8_t reserved[56];
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} __attribute__ (( packed ));
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/**
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* Queue data buffer size
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*
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* In theory, we may specify the size of receive buffers. However,
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* the original version of the device seems not to have a parameter
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* for this, and assumes the use of half-page (2kB) buffers. Choose
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* to use this as the buffer size, on the assumption that older
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* devices will not support any other buffer size.
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*/
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#define GVE_BUF_SIZE ( GVE_PAGE_SIZE / 2 )
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/** Number of data buffers per page */
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#define GVE_BUF_PER_PAGE ( GVE_PAGE_SIZE / GVE_BUF_SIZE )
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/**
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* Queue page list
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*
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* The device uses preregistered pages for fast-path DMA operations
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* (i.e. transmit and receive buffers). A list of device addresses
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* for each page must be registered before the transmit or receive
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* queue is created, and cannot subsequently be modified.
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*
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* The Linux driver allocates pages as DMA_TO_DEVICE or
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* DMA_FROM_DEVICE as appropriate, and uses dma_sync_single_for_cpu()
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* etc to ensure that data is copied to/from bounce buffers as needed.
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*
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* Unfortunately there is no such sync operation available within our
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* DMA API, since we are constrained by the limitations imposed by
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* EFI_PCI_IO_PROTOCOL. There is no way to synchronise a buffer
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* without also [un]mapping it, and no way to force the reuse of the
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* same device address for a subsequent remapping. We are therefore
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* constrained to use only DMA-coherent buffers, since this is the
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* only way we can repeatedly reuse the same device address.
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*
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* Newer versions of the gVNIC device support "raw DMA addressing
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* (RDA)", which is essentially a prebuilt queue page list covering
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* the whole of the guest address space. Unfortunately we cannot rely
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* on this, since older versions will not support it.
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*
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* Experimentation suggests that the device will accept a request to
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* create a queue page list covering the whole of the guest address
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* space via two giant "pages" of 2^63 bytes each. However,
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* experimentation also suggests that the device will accept any old
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* garbage value as the "page size". In the total absence of any
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* documentation, it is probably unsafe to conclude that the device is
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* bothering to look at or respect the "page size" parameter: it is
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* most likely just presuming the use of 4kB pages.
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*/
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struct gve_qpl {
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/** Page addresses */
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userptr_t data;
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/** Page mapping */
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struct dma_mapping map;
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/** Number of pages */
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unsigned int count;
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/** Queue page list ID */
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unsigned int id;
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};
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/**
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* Maximum number of transmit buffers
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*
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* This is a policy decision.
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*/
|
||||
#define GVE_TX_FILL 8
|
||||
|
||||
/** Transmit queue page list ID */
|
||||
#define GVE_TX_QPL 0x18ae5458
|
||||
|
||||
/** Tranmsit queue interrupt channel */
|
||||
#define GVE_TX_IRQ 0
|
||||
|
||||
/** A transmit or receive buffer descriptor */
|
||||
struct gve_buffer {
|
||||
/** Address (within queue page list address space) */
|
||||
uint64_t addr;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** A transmit packet descriptor */
|
||||
struct gve_tx_packet {
|
||||
/** Type */
|
||||
uint8_t type;
|
||||
/** Reserved */
|
||||
uint8_t reserved_a[2];
|
||||
/** Number of descriptors in this packet */
|
||||
uint8_t count;
|
||||
/** Total length of this packet */
|
||||
uint16_t total;
|
||||
/** Length of this descriptor */
|
||||
uint16_t len;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** A transmit descriptor */
|
||||
struct gve_tx_descriptor {
|
||||
/** Packet descriptor */
|
||||
struct gve_tx_packet pkt;
|
||||
/** Buffer descriptor */
|
||||
struct gve_buffer buf;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Start of packet transmit descriptor type */
|
||||
#define GVE_TX_TYPE_START 0x00
|
||||
|
||||
/** Continuation of packet transmit descriptor type */
|
||||
#define GVE_TX_TYPE_CONT 0x20
|
||||
|
||||
/**
|
||||
* Maximum number of receive buffers
|
||||
*
|
||||
* This is a policy decision.
|
||||
*/
|
||||
#define GVE_RX_FILL 16
|
||||
|
||||
/** Receive queue page list ID */
|
||||
#define GVE_RX_QPL 0x18ae5258
|
||||
|
||||
/** Receive queue interrupt channel */
|
||||
#define GVE_RX_IRQ 1
|
||||
|
||||
/** A receive descriptor */
|
||||
struct gve_rx_descriptor {
|
||||
/** Buffer descriptor */
|
||||
struct gve_buffer buf;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** A receive packet descriptor */
|
||||
struct gve_rx_packet {
|
||||
/** Length */
|
||||
uint16_t len;
|
||||
/** Flags */
|
||||
uint8_t flags;
|
||||
/** Sequence number */
|
||||
uint8_t seq;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Receive error */
|
||||
#define GVE_RXF_ERROR 0x08
|
||||
|
||||
/** Receive packet continues into next descriptor */
|
||||
#define GVE_RXF_MORE 0x20
|
||||
|
||||
/** Receive sequence number mask */
|
||||
#define GVE_RX_SEQ_MASK 0x07
|
||||
|
||||
/** A receive completion descriptor */
|
||||
struct gve_rx_completion {
|
||||
/** Reserved */
|
||||
uint8_t reserved[60];
|
||||
/** Packet descriptor */
|
||||
struct gve_rx_packet pkt;
|
||||
} __attribute__ (( packed ));
|
||||
|
||||
/** Padding at the start of all received packets */
|
||||
#define GVE_RX_PAD 2
|
||||
|
||||
/** A descriptor queue */
|
||||
struct gve_queue {
|
||||
/** Descriptor ring */
|
||||
userptr_t desc;
|
||||
/** Completion ring */
|
||||
userptr_t cmplt;
|
||||
/** Queue resources */
|
||||
struct gve_resources *res;
|
||||
|
||||
/** Queue type */
|
||||
const struct gve_queue_type *type;
|
||||
/** Number of descriptors (must be a power of two) */
|
||||
unsigned int count;
|
||||
/** Maximum fill level (must be a power of two) */
|
||||
unsigned int fill;
|
||||
|
||||
/** Descriptor mapping */
|
||||
struct dma_mapping desc_map;
|
||||
/** Completion mapping */
|
||||
struct dma_mapping cmplt_map;
|
||||
/** Queue resources mapping */
|
||||
struct dma_mapping res_map;
|
||||
|
||||
/** Doorbell register */
|
||||
volatile uint32_t *db;
|
||||
/** Event counter */
|
||||
struct gve_event *event;
|
||||
|
||||
/** Producer counter */
|
||||
uint32_t prod;
|
||||
/** Consumer counter */
|
||||
uint32_t cons;
|
||||
|
||||
/** Queue page list */
|
||||
struct gve_qpl qpl;
|
||||
};
|
||||
|
||||
/** A descriptor queue type */
|
||||
struct gve_queue_type {
|
||||
/** Name */
|
||||
const char *name;
|
||||
/**
|
||||
* Populate command parameters to create queue
|
||||
*
|
||||
* @v queue Descriptor queue
|
||||
* @v cmd Admin queue command
|
||||
*/
|
||||
void ( * param ) ( struct gve_queue *queue,
|
||||
union gve_admin_command *cmd );
|
||||
/** Queue page list ID */
|
||||
uint32_t qpl;
|
||||
/** Interrupt channel */
|
||||
uint8_t irq;
|
||||
/** Maximum fill level */
|
||||
uint8_t fill;
|
||||
/** Descriptor size */
|
||||
uint8_t desc_len;
|
||||
/** Completion size */
|
||||
uint8_t cmplt_len;
|
||||
/** Command to create queue */
|
||||
uint8_t create;
|
||||
/** Command to destroy queue */
|
||||
uint8_t destroy;
|
||||
};
|
||||
|
||||
/** A Google Virtual Ethernet NIC */
|
||||
struct gve_nic {
|
||||
/** Configuration registers */
|
||||
void *cfg;
|
||||
/** Doorbell registers */
|
||||
void *db;
|
||||
/** PCI revision */
|
||||
uint8_t revision;
|
||||
/** Network device */
|
||||
struct net_device *netdev;
|
||||
/** DMA device */
|
||||
struct dma_device *dma;
|
||||
|
||||
/** Admin queue */
|
||||
struct gve_admin admin;
|
||||
/** Interrupt channels */
|
||||
struct gve_irqs irqs;
|
||||
/** Event counters */
|
||||
struct gve_events events;
|
||||
/** Scratch buffer */
|
||||
struct gve_scratch scratch;
|
||||
|
||||
/** Transmit queue */
|
||||
struct gve_queue tx;
|
||||
/** Receive queue */
|
||||
struct gve_queue rx;
|
||||
/** Transmit I/O buffers */
|
||||
struct io_buffer *tx_iobuf[GVE_TX_FILL];
|
||||
/** Receive sequence number */
|
||||
unsigned int seq;
|
||||
|
||||
/** Startup process */
|
||||
struct process startup;
|
||||
/** Startup process retry counter */
|
||||
unsigned int retries;
|
||||
/** Reset recovery watchdog timer */
|
||||
struct retry_timer watchdog;
|
||||
/** Reset recovery recorded activity counter */
|
||||
uint32_t activity;
|
||||
};
|
||||
|
||||
/** Maximum time to wait for admin queue commands */
|
||||
#define GVE_ADMIN_MAX_WAIT_MS 500
|
||||
|
||||
/** Maximum number of times to reattempt device reset */
|
||||
#define GVE_RESET_MAX_RETRY 5
|
||||
|
||||
/** Time between reset recovery checks */
|
||||
#define GVE_WATCHDOG_TIMEOUT ( 1 * TICKS_PER_SEC )
|
||||
|
||||
#endif /* _GVE_H */
|
||||
@ -224,6 +224,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
|
||||
#define ERRFILE_ecam ( ERRFILE_DRIVER | 0x00d30000 )
|
||||
#define ERRFILE_pcibridge ( ERRFILE_DRIVER | 0x00d40000 )
|
||||
#define ERRFILE_mnpnet ( ERRFILE_DRIVER | 0x00d50000 )
|
||||
#define ERRFILE_gve ( ERRFILE_DRIVER | 0x00d60000 )
|
||||
|
||||
#define ERRFILE_aoe ( ERRFILE_NET | 0x00000000 )
|
||||
#define ERRFILE_arp ( ERRFILE_NET | 0x00010000 )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user