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https://sourceware.org/git/glibc.git
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2ba9801d9f
This patch fixes two problems with audit:
1. The DL_OFFSET_RV_VPCS offset was mixed up with DL_OFFSET_RG_VPCS,
resulting in x2 register value nulling in RG structure.
2. We need to preserve the x8 register before function call, but
don't have to save it's new value and restore it before return.
Anyway the final restore was using OFFSET_RV instead of OFFSET_RG value
which is wrong (althoug doesn't affect anything).
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
(cherry picked from commit eb4181e9f4)
342 lines
9.8 KiB
ArmAsm
342 lines
9.8 KiB
ArmAsm
/* Copyright (C) 2005-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation; either version 2.1 of the
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License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <libc-symbols.h>
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#include "dl-link.h"
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#define ip0 x16
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#define ip0l PTR_REG (16)
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#define ip1 x17
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#define lr x30
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/* RELA relocatons are 3 pointers */
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#define RELA_SIZE (PTR_SIZE * 3)
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.text
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.globl _dl_runtime_resolve
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.type _dl_runtime_resolve, #function
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cfi_startproc
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.align 2
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_dl_runtime_resolve:
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BTI_C
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/* AArch64 we get called with:
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ip0 &PLTGOT[2]
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ip1 temp(dl resolver entry point)
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[sp, #8] lr
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[sp, #0] &PLTGOT[n]
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*/
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cfi_rel_offset (lr, 8)
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/* Note: Saving x9 is not required by the ABI but the assembler requires
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the immediate values of operand 3 to be a multiple of 16 */
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stp x8, x9, [sp, #-(80+8*16)]!
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cfi_adjust_cfa_offset (80+8*16)
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cfi_rel_offset (x8, 0)
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cfi_rel_offset (x9, 8)
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stp x6, x7, [sp, #16]
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cfi_rel_offset (x6, 16)
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cfi_rel_offset (x7, 24)
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stp x4, x5, [sp, #32]
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cfi_rel_offset (x4, 32)
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cfi_rel_offset (x5, 40)
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stp x2, x3, [sp, #48]
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cfi_rel_offset (x2, 48)
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cfi_rel_offset (x3, 56)
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stp x0, x1, [sp, #64]
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cfi_rel_offset (x0, 64)
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cfi_rel_offset (x1, 72)
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stp q0, q1, [sp, #(80+0*16)]
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cfi_rel_offset (q0, 80+0*16)
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cfi_rel_offset (q1, 80+1*16)
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stp q2, q3, [sp, #(80+2*16)]
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cfi_rel_offset (q0, 80+2*16)
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cfi_rel_offset (q1, 80+3*16)
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stp q4, q5, [sp, #(80+4*16)]
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cfi_rel_offset (q0, 80+4*16)
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cfi_rel_offset (q1, 80+5*16)
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stp q6, q7, [sp, #(80+6*16)]
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cfi_rel_offset (q0, 80+6*16)
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cfi_rel_offset (q1, 80+7*16)
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/* Get pointer to linker struct. */
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ldr PTR_REG (0), [ip0, #-PTR_SIZE]
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/* Prepare to call _dl_fixup(). */
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ldr x1, [sp, 80+8*16] /* Recover &PLTGOT[n] */
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sub x1, x1, ip0
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add x1, x1, x1, lsl #1
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lsl x1, x1, #3
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sub x1, x1, #(RELA_SIZE<<3)
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lsr x1, x1, #3
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/* Call fixup routine. */
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bl _dl_fixup
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/* Save the return. */
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mov ip0, x0
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/* Get arguments and return address back. */
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ldp q0, q1, [sp, #(80+0*16)]
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ldp q2, q3, [sp, #(80+2*16)]
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ldp q4, q5, [sp, #(80+4*16)]
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ldp q6, q7, [sp, #(80+6*16)]
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ldp x0, x1, [sp, #64]
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ldp x2, x3, [sp, #48]
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ldp x4, x5, [sp, #32]
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ldp x6, x7, [sp, #16]
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ldp x8, x9, [sp], #(80+8*16)
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cfi_adjust_cfa_offset (-(80+8*16))
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ldp ip1, lr, [sp], #16
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cfi_adjust_cfa_offset (-16)
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/* Jump to the newly found address. */
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br ip0
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cfi_endproc
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.size _dl_runtime_resolve, .-_dl_runtime_resolve
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#ifndef PROF
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.globl _dl_runtime_profile
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.type _dl_runtime_profile, #function
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cfi_startproc
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.align 2
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_dl_runtime_profile:
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# if HAVE_AARCH64_PAC_RET
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PACIASP
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cfi_window_save
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# else
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BTI_C
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# endif
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/* AArch64 we get called with:
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ip0 &PLTGOT[2]
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ip1 temp(dl resolver entry point)
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[sp, #8] lr
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[sp, #0] &PLTGOT[n]
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Stack frame layout:
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[sp, #...] lr
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[sp, #...] &PLTGOT[n]
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[sp, #256] La_aarch64_regs
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[sp, #48] La_aarch64_retval
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[sp, #40] frame size return from pltenter
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[sp, #32] dl_profile_call saved x1
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[sp, #24] dl_profile_call saved x0
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[sp, #16] t1
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[sp, #0] x29, lr <- x29
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*/
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# define OFFSET_T1 16
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# define OFFSET_SAVED_CALL_X0 OFFSET_T1 + 8
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# define OFFSET_FS OFFSET_SAVED_CALL_X0 + 16
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# define OFFSET_RV OFFSET_FS + 8
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# define OFFSET_RG OFFSET_RV + DL_SIZEOF_RV
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# define SF_SIZE OFFSET_RG + DL_SIZEOF_RG
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# define OFFSET_PLTGOTN SF_SIZE
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# define OFFSET_LR OFFSET_PLTGOTN + 8
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/* Save arguments. */
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sub sp, sp, #SF_SIZE
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cfi_adjust_cfa_offset (SF_SIZE)
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stp x29, x30, [SP, #0]
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mov x29, sp
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cfi_def_cfa_register (x29)
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cfi_rel_offset (x29, 0)
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cfi_rel_offset (lr, 8)
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stp x0, x1, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*0]
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cfi_rel_offset (x0, OFFSET_RG + DL_OFFSET_RG_X0 + 16*0 + 0)
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cfi_rel_offset (x1, OFFSET_RG + DL_OFFSET_RG_X0 + 16*0 + 8)
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stp x2, x3, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*1]
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cfi_rel_offset (x2, OFFSET_RG + DL_OFFSET_RG_X0 + 16*1 + 0)
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cfi_rel_offset (x3, OFFSET_RG + DL_OFFSET_RG_X0 + 16*1 + 8)
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stp x4, x5, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*2]
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cfi_rel_offset (x4, OFFSET_RG + DL_OFFSET_RG_X0 + 16*2 + 0)
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cfi_rel_offset (x5, OFFSET_RG + DL_OFFSET_RG_X0 + 16*2 + 8)
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stp x6, x7, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*3]
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cfi_rel_offset (x6, OFFSET_RG + DL_OFFSET_RG_X0 + 16*3 + 0)
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cfi_rel_offset (x7, OFFSET_RG + DL_OFFSET_RG_X0 + 16*3 + 8)
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str x8, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*4 + 0]
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cfi_rel_offset (x8, OFFSET_RG + DL_OFFSET_RG_X0 + 16*4 + 0)
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/* Note 8 bytes of padding is in the stack frame for alignment */
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stp q0, q1, [X29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*0]
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cfi_rel_offset (q0, OFFSET_RG + DL_OFFSET_RG_V0 + 32*0)
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cfi_rel_offset (q1, OFFSET_RG + DL_OFFSET_RG_V0 + 32*0 + 16)
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stp q2, q3, [X29, #OFFSET_RG+ DL_OFFSET_RG_V0 + 32*1]
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cfi_rel_offset (q2, OFFSET_RG + DL_OFFSET_RG_V0 + 32*1 + 0)
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cfi_rel_offset (q3, OFFSET_RG + DL_OFFSET_RG_V0 + 32*1 + 16)
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stp q4, q5, [X29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*2]
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cfi_rel_offset (q4, OFFSET_RG + DL_OFFSET_RG_V0 + 32*2 + 0)
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cfi_rel_offset (q5, OFFSET_RG + DL_OFFSET_RG_V0 + 32*2 + 16)
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stp q6, q7, [X29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*3]
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cfi_rel_offset (q6, OFFSET_RG + DL_OFFSET_RG_V0 + 32*3 + 0)
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cfi_rel_offset (q7, OFFSET_RG + DL_OFFSET_RG_V0 + 32*3 + 16)
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/* No APCS extension supported. */
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str xzr, [X29, #OFFSET_RG + DL_OFFSET_RG_VPCS]
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add x0, x29, #SF_SIZE + 16
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ldr x1, [x29, #OFFSET_LR]
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stp x0, x1, [x29, #OFFSET_RG + DL_OFFSET_RG_SP]
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/* Get pointer to linker struct. */
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ldr PTR_REG (0), [ip0, #-PTR_SIZE]
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/* Prepare to call _dl_profile_fixup(). */
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ldr x1, [x29, OFFSET_PLTGOTN] /* Recover &PLTGOT[n] */
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sub x1, x1, ip0
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add x1, x1, x1, lsl #1
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lsl x1, x1, #3
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sub x1, x1, #(RELA_SIZE<<3)
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lsr x1, x1, #3
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stp x0, x1, [x29, #OFFSET_SAVED_CALL_X0]
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/* Set up extra args for _dl_profile_fixup */
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ldr x2, [x29, #OFFSET_LR] /* load saved LR */
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add x3, x29, #OFFSET_RG /* address of La_aarch64_reg */
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add x4, x29, #OFFSET_FS /* address of framesize */
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bl _dl_profile_fixup
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ldr ip0l, [x29, #OFFSET_FS] /* framesize == 0 */
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cmp ip0l, #0
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bge 1f
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cfi_remember_state
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/* Save the return. */
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mov ip0, x0
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/* Get arguments and return address back. */
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ldp x0, x1, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*0]
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ldp x2, x3, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*1]
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ldp x4, x5, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*2]
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ldp x6, x7, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*3]
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ldr x8, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*4]
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ldp q0, q1, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*0]
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ldp q2, q3, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*1]
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ldp q4, q5, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*2]
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ldp q6, q7, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*3]
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cfi_def_cfa_register (sp)
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ldp x29, x30, [x29, #0]
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cfi_restore(x29)
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cfi_restore(x30)
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# if HAVE_AARCH64_PAC_RET
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add sp, sp, SF_SIZE
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cfi_adjust_cfa_offset (-SF_SIZE)
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AUTIASP
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cfi_window_save
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add sp, sp, 16
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cfi_adjust_cfa_offset (-16)
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# else
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add sp, sp, SF_SIZE + 16
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cfi_adjust_cfa_offset (- SF_SIZE - 16)
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# endif
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/* Jump to the newly found address. */
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br ip0
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cfi_restore_state
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1:
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/* The new frame size is in ip0. */
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sub PTR_REG (1), PTR_REG (29), ip0l
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and sp, x1, #0xfffffffffffffff0
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str x0, [x29, #OFFSET_T1]
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mov x0, sp
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add x1, x29, #SF_SIZE + 16
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mov x2, ip0
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bl memcpy
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ldr ip0, [x29, #OFFSET_T1]
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/* Call the function. */
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ldp x0, x1, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*0]
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ldp x2, x3, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*1]
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ldp x4, x5, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*2]
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ldp x6, x7, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*3]
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ldr x8, [x29, #OFFSET_RG + DL_OFFSET_RG_X0 + 16*4]
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ldp q0, q1, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*0]
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ldp q2, q3, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*1]
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ldp q4, q5, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*2]
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ldp q6, q7, [x29, #OFFSET_RG + DL_OFFSET_RG_V0 + 32*3]
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blr ip0
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stp x0, x1, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*0]
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stp x2, x3, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*1]
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stp x4, x5, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*2]
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stp x6, x7, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*3]
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stp q0, q1, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*0]
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stp q2, q3, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*1]
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stp q4, q5, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*2]
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stp q6, q7, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*3]
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str xzr, [X29, #OFFSET_RV + DL_OFFSET_RV_VPCS]
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/* Setup call to pltexit */
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ldp x0, x1, [x29, #OFFSET_SAVED_CALL_X0]
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add x2, x29, #OFFSET_RG
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add x3, x29, #OFFSET_RV
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bl _dl_audit_pltexit
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ldp x0, x1, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*0]
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ldp x2, x3, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*1]
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ldp x4, x5, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*2]
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ldp x6, x7, [x29, #OFFSET_RV + DL_OFFSET_RV_X0 + 16*3]
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ldp q0, q1, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*0]
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ldp q2, q3, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*1]
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ldp q4, q5, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*2]
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ldp q6, q7, [x29, #OFFSET_RV + DL_OFFSET_RV_V0 + 32*3]
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/* LR from within La_aarch64_reg */
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ldr lr, [x29, #OFFSET_RG + DL_OFFSET_RG_LR]
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cfi_restore(lr)
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# if HAVE_AARCH64_PAC_RET
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/* Note: LR restored from La_aarch64_reg has no PAC. */
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cfi_window_save
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# endif
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mov sp, x29
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cfi_def_cfa_register (sp)
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ldr x29, [x29, #0]
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cfi_restore(x29)
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add sp, sp, SF_SIZE + 16
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cfi_adjust_cfa_offset (- SF_SIZE - 16)
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br lr
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cfi_endproc
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.size _dl_runtime_profile, .-_dl_runtime_profile
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#endif
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.previous
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