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aarch64: Remove non-temporal load/stores from oryon-1's memcpy
The hardware architects have a new recommendation not to use non-temporal load/stores for memcpy. This patch removes this path. I found there was no difference in the memcpy speed with/without non-temporal load/stores either. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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@ -160,46 +160,6 @@ L(copy96):
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.p2align 6
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L(copy_long):
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/* On oryon1 cores, large memcpy's are helped by using ldnp/stnp.
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This loop is identical to the one below it but using ldnp/stnp
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instructions. For loops that are less than 32768 bytes,
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the ldnp/stnp instructions will not help and will cause a slow
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down so only use the ldnp/stnp loop for the largest sizes. */
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cmp count, #32768
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b.lo L(copy_long_without_nontemp)
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and tmp1, dstin, 15
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bic dst, dstin, 15
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ldnp D_l, D_h, [src]
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sub src, src, tmp1
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add count, count, tmp1 /* Count is now 16 too large. */
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ldnp A_l, A_h, [src, 16]
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stnp D_l, D_h, [dstin]
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ldnp B_l, B_h, [src, 32]
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ldnp C_l, C_h, [src, 48]
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ldnp D_l, D_h, [src, 64]
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add src, src, #64
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subs count, count, 128 + 16 /* Test and readjust count. */
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L(nontemp_loop64):
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tbz src, #6, 1f
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1:
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stnp A_l, A_h, [dst, 16]
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ldnp A_l, A_h, [src, 16]
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stnp B_l, B_h, [dst, 32]
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ldnp B_l, B_h, [src, 32]
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stnp C_l, C_h, [dst, 48]
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ldnp C_l, C_h, [src, 48]
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stnp D_l, D_h, [dst, 64]
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ldnp D_l, D_h, [src, 64]
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add src, src, #64
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add dst, dst, #64
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subs count, count, 64
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b.hi L(nontemp_loop64)
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b L(last64)
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L(copy_long_without_nontemp):
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and tmp1, dstin, 15
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bic dst, dstin, 15
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ldp D_l, D_h, [src]
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