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AArch64: Add asymmetric faulting mode for tag violations in mem.tagging tunable

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The new asymmetric mode is available when HWCAP2_MTE3 is set (support is
available), bit2 is set in the tunable (user request per application),
and the system is configured such that the asymmetric mode is preferred over
sync or async (per-cpu system-wide setting).

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
This commit is contained in:
Tejas Belagod 2022-06-27 18:00:50 +00:00 committed by Szabolcs Nagy
parent 71d87d85bf
commit e9dd368296
2 changed files with 10 additions and 1 deletions
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3
manual/tunables.texi
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@ -602,6 +602,9 @@ Bit 1 enables precise faulting mode for tag violations on systems that
support deferred tag violation reporting. This may cause programs
to run more slowly.
Bit 2 enables either precise or deferred faulting mode for tag violations
whichever is preferred by the system.
Other bits are currently reserved.
@Theglibc{} startup code will automatically enable memory tagging

8
sysdeps/unix/sysv/linux/aarch64/cpu-features.c
View File

@ -108,7 +108,13 @@ init_cpu_features (struct cpu_features *cpu_features)
TUNABLE_SET (glibc, mem, tagging, cpu_features->mte_state);
# endif
if (cpu_features->mte_state & 2)
if (cpu_features->mte_state & 4)
/* Enable choosing system-preferred faulting mode. */
__prctl (PR_SET_TAGGED_ADDR_CTRL,
(PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC
| MTE_ALLOWED_TAGS),
0, 0, 0);
else if (cpu_features->mte_state & 2)
__prctl (PR_SET_TAGGED_ADDR_CTRL,
(PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS),
0, 0, 0);