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x86-64: Check Prefer_FSRM in ifunc-memmove.h
Although the REP MOVSB implementations of memmove, memcpy and mempcpy aren't used by the current processors, this patch adds Prefer_FSRM check in ifunc-memmove.h so that they can be used in the future. * sysdeps/x86/cpu-features.h (bit_arch_Prefer_FSRM): New. (index_arch_Prefer_FSRM): Likewise. * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): Also check Prefer_FSRM. * sysdeps/x86_64/multiarch/ifunc-memmove.h (IFUNC_SELECTOR): Also return OPTIMIZE (erms) for Prefer_FSRM.
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@ -1,3 +1,12 @@
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2018-05-21 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/x86/cpu-features.h (bit_arch_Prefer_FSRM): New.
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(index_arch_Prefer_FSRM): Likewise.
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* sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)):
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Also check Prefer_FSRM.
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* sysdeps/x86_64/multiarch/ifunc-memmove.h (IFUNC_SELECTOR):
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Also return OPTIMIZE (erms) for Prefer_FSRM.
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2018-05-21 H.J. Lu <hongjiu.lu@intel.com>
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2018-05-21 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New.
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* sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New.
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@ -40,6 +40,7 @@
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#define bit_arch_Prefer_No_AVX512 (1 << 20)
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#define bit_arch_Prefer_No_AVX512 (1 << 20)
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#define bit_arch_MathVec_Prefer_No_AVX512 (1 << 21)
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#define bit_arch_MathVec_Prefer_No_AVX512 (1 << 21)
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#define bit_arch_XSAVEC_Usable (1 << 22)
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#define bit_arch_XSAVEC_Usable (1 << 22)
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#define bit_arch_Prefer_FSRM (1 << 23)
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/* CPUID Feature flags. */
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/* CPUID Feature flags. */
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@ -264,6 +265,7 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define index_arch_Prefer_No_AVX512 FEATURE_INDEX_1
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# define index_arch_Prefer_No_AVX512 FEATURE_INDEX_1
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# define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_1
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# define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_1
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# define index_arch_XSAVEC_Usable FEATURE_INDEX_1
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# define index_arch_XSAVEC_Usable FEATURE_INDEX_1
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# define index_arch_Prefer_FSRM FEATURE_INDEX_1
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#endif /* !__ASSEMBLER__ */
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#endif /* !__ASSEMBLER__ */
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@ -241,6 +241,8 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp)
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CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (n, cpu_features,
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CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (n, cpu_features,
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Slow_SSE4_2, SSE4_2,
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Slow_SSE4_2, SSE4_2,
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disable, 11);
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disable, 11);
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CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features, Prefer_FSRM,
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disable, 11);
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break;
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break;
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case 13:
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case 13:
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if (disable)
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if (disable)
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@ -41,7 +41,8 @@ IFUNC_SELECTOR (void)
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{
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{
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const struct cpu_features* cpu_features = __get_cpu_features ();
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const struct cpu_features* cpu_features = __get_cpu_features ();
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if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS))
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if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS)
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|| CPU_FEATURES_ARCH_P (cpu_features, Prefer_FSRM))
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return OPTIMIZE (erms);
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return OPTIMIZE (erms);
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if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
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if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
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