mirrors/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-11-24 02:03:35 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

Correct Intel processor level type mask from CPUID

Browse Source 
Intel CPUID with EAX == 11 returns:

ECX Bits 07 - 00: Level number. Same value in ECX input.
    Bits 15 - 08: Level type.
    ^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
    Bits 31 - 16: Reserved.

Intel processor level type mask should be 0xff00, not 0xff0.

	[BZ #20119]
	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
	processor level type mask for CPUID with EAX == 11.
This commit is contained in:
H.J. Lu 2016-05-19 10:02:36 -07:00
parent 7c08d791ee
commit de71e0421b
2 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ChangeLog
View File

@ -1,3 +1,9 @@
2016-05-19 H.J. Lu <hongjiu.lu@intel.com>
[BZ #20119]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
processor level type mask for CPUID with EAX == 11.
2016-05-19 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting

2
sysdeps/x86/cacheinfo.c
View File

@ -552,7 +552,7 @@ init_cacheinfo (void)
__cpuid_count (11, i++, eax, ebx, ecx, edx);
int shipped = ebx & 0xff;
int type = ecx & 0xff0;
int type = ecx & 0xff00;
if (shipped == 0 || type == 0)
break;
else if (type == 0x200)