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AArch64: Optimize memcmp
Rewrite memcmp to improve performance. On small and medium inputs performance is 10-20% better. Large inputs use a SIMD loop processing 64 bytes per iteration, which is 30-50% faster depending on the size. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
This commit is contained in:
Wilco Dijkstra
parent
d120fb9941
commit
b51eb35c57
@ -22,105 +22,79 @@
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses.
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* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
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*/
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/* Parameters and result. */
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#define src1 x0
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#define src2 x1
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#define limit x2
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#define result w0
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/* Internal variables. */
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#define data1 x3
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#define data1w w3
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#define data1h x4
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#define data2 x5
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#define data2w w5
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#define data2h x6
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#define tmp1 x7
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#define tmp2 x8
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#define data2 x4
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#define data2w w4
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#define data3 x5
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#define data3w w5
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#define data4 x6
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#define data4w w6
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#define tmp x6
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#define src1end x7
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#define src2end x8
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ENTRY_ALIGN (memcmp, 6)
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ENTRY (memcmp)
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PTR_ARG (0)
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PTR_ARG (1)
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SIZE_ARG (2)
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subs limit, limit, 16
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cmp limit, 16
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b.lo L(less16)
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ldp data1, data1h, [src1], 16
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ldp data2, data2h, [src2], 16
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ldp data1, data3, [src1]
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ldp data2, data4, [src2]
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ccmp data1, data2, 0, ne
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ccmp data1h, data2h, 0, eq
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b.ne L(return64)
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ccmp data3, data4, 0, eq
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b.ne L(return2)
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subs limit, limit, 16
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add src1end, src1, limit
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add src2end, src2, limit
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cmp limit, 32
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b.ls L(last_bytes)
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cmp limit, 112
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b.lo L(loop16)
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cmp limit, 160
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b.hs L(loop_align)
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sub limit, limit, 32
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and tmp1, src1, 15
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add limit, limit, tmp1
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sub src1, src1, tmp1
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sub src2, src2, tmp1
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subs limit, limit, 48
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/* Compare 128 up bytes using aligned access. */
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.p2align 4
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L(loop64):
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ldp data1, data1h, [src1]
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ldp data2, data2h, [src2]
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L(loop32):
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ldp data1, data3, [src1, 16]
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ldp data2, data4, [src2, 16]
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cmp data1, data2
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ccmp data1h, data2h, 0, eq
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b.ne L(return64)
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ccmp data3, data4, 0, eq
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b.ne L(return2)
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cmp limit, 16
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b.ls L(last_bytes)
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ldp data1, data1h, [src1, 16]
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ldp data2, data2h, [src2, 16]
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ldp data1, data3, [src1, 32]
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ldp data2, data4, [src2, 32]
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cmp data1, data2
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ccmp data1h, data2h, 0, eq
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b.ne L(return64)
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ccmp data3, data4, 0, eq
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b.ne L(return2)
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add src1, src1, 32
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add src2, src2, 32
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L(last64):
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subs limit, limit, 32
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b.hi L(loop32)
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ldp data1, data1h, [src1, 32]
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ldp data2, data2h, [src2, 32]
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cmp data1, data2
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ccmp data1h, data2h, 0, eq
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b.ne L(return64)
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ldp data1, data1h, [src1, 48]
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ldp data2, data2h, [src2, 48]
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cmp data1, data2
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ccmp data1h, data2h, 0, eq
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b.ne L(return64)
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subs limit, limit, 64
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add src1, src1, 64
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add src2, src2, 64
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b.pl L(loop64)
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adds limit, limit, 48
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b.lo L(last_bytes)
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L(loop16):
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ldp data1, data1h, [src1], 16
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ldp data2, data2h, [src2], 16
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cmp data1, data2
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ccmp data1h, data2h, 0, eq
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b.ne L(return64)
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subs limit, limit, 16
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b.hi L(loop16)
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/* Compare last 1-16 bytes using unaligned access. */
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L(last_bytes):
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add src1, src1, limit
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add src2, src2, limit
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ldp data1, data1h, [src1]
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ldp data2, data2h, [src2]
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ldp data1, data3, [src1end, -16]
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ldp data2, data4, [src2end, -16]
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L(return2):
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cmp data1, data2
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csel data1, data1, data3, ne
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csel data2, data2, data4, ne
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/* Compare data bytes and set return value to 0, -1 or 1. */
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L(return64):
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cmp data1, data2
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csel data1, data1, data1h, ne
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csel data2, data2, data2h, ne
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L(return):
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#ifndef __AARCH64EB__
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rev data1, data1
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@ -133,45 +107,98 @@ L(return):
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.p2align 4
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L(less16):
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adds limit, limit, 8
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b.lo L(less8) //lo:<
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add src1end, src1, limit
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add src2end, src2, limit
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tbz limit, 3, L(less8)
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ldr data1, [src1]
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ldr data2, [src2]
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/* equal 8 optimized */
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ccmp data1, data2, 0, ne
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b.ne L(return)
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ldr data1, [src1, limit]
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ldr data2, [src2, limit]
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b L(return)
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ldr data3, [src1end, -8]
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ldr data4, [src2end, -8]
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b L(return2)
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.p2align 4
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L(less8):
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adds limit, limit, 4
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b.lo L(less4)
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tbz limit, 2, L(less4)
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ldr data1w, [src1]
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ldr data2w, [src2]
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ccmp data1w, data2w, 0, ne
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ldr data3w, [src1end, -4]
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ldr data4w, [src2end, -4]
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b L(return2)
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L(less4):
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tbz limit, 1, L(less2)
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ldrh data1w, [src1]
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ldrh data2w, [src2]
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cmp data1w, data2w
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b.ne L(return)
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ldr data1w, [src1, limit]
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ldr data2w, [src2, limit]
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b L(return)
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L(less2):
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mov result, 0
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tbz limit, 0, L(return_zero)
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ldrb data1w, [src1end, -1]
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ldrb data2w, [src2end, -1]
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sub result, data1w, data2w
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L(return_zero):
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ret
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L(loop_align):
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ldp data1, data3, [src1, 16]
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ldp data2, data4, [src2, 16]
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cmp data1, data2
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ccmp data3, data4, 0, eq
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b.ne L(return2)
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/* Align src2 and adjust src1, src2 and limit. */
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and tmp, src2, 15
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sub tmp, tmp, 16
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sub src2, src2, tmp
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add limit, limit, tmp
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sub src1, src1, tmp
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sub limit, limit, 64 + 16
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.p2align 4
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L(less4):
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adds limit, limit, 4
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b.eq L(ret_0)
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L(loop64):
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ldr q0, [src1, 16]
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ldr q1, [src2, 16]
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subs limit, limit, 64
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ldr q2, [src1, 32]
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ldr q3, [src2, 32]
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eor v0.16b, v0.16b, v1.16b
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eor v1.16b, v2.16b, v3.16b
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ldr q2, [src1, 48]
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ldr q3, [src2, 48]
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umaxp v0.16b, v0.16b, v1.16b
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ldr q4, [src1, 64]!
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ldr q5, [src2, 64]!
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eor v1.16b, v2.16b, v3.16b
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eor v2.16b, v4.16b, v5.16b
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umaxp v1.16b, v1.16b, v2.16b
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umaxp v0.16b, v0.16b, v1.16b
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umaxp v0.16b, v0.16b, v0.16b
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fmov tmp, d0
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ccmp tmp, 0, 0, hi
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b.eq L(loop64)
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L(byte_loop):
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ldrb data1w, [src1], 1
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ldrb data2w, [src2], 1
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subs limit, limit, 1
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ccmp data1w, data2w, 0, ne /* NZCV = 0b0000. */
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b.eq L(byte_loop)
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sub result, data1w, data2w
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ret
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L(ret_0):
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mov result, 0
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/* If equal, process last 1-64 bytes using scalar loop. */
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add limit, limit, 64 + 16
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cbz tmp, L(last64)
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/* Determine the 8-byte aligned offset of the first difference. */
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#ifdef __AARCH64EB__
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rev16 tmp, tmp
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#endif
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rev tmp, tmp
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clz tmp, tmp
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bic tmp, tmp, 7
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sub tmp, tmp, 48
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ldr data1, [src1, tmp]
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ldr data2, [src2, tmp]
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#ifndef __AARCH64EB__
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rev data1, data1
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rev data2, data2
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#endif
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mov result, 1
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cmp data1, data2
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cneg result, result, lo
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ret
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END (memcmp)
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