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powerpc: Fix incorrect cache line size load in memset (bug 26332)

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__GLRO loaded the word after the requested variable on big-endian
PowerPC, where LOWORD is 4.  This can cause the memset implement
go wrong because the masking with the cache line size produces
wrong results, particularly if the loaded value happens to be 1.

The __GLRO macro is not used in any place where loading the lower
32-bit word of a 64-bit value is desired, so the +4 offset is always
wrong.

Fixes commit 18363b4f01
("powerpc: Move cache line size to rtld_global_ro") and bug 26332.

Reviewed-by: Carlos O'Donell <carlos@redhat.com>
This commit is contained in:
Florian Weimer 2020-08-03 18:07:19 +02:00
parent 783fdd969f
commit 7650321ce0
1 changed files with 2 additions and 2 deletions
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4
sysdeps/powerpc/powerpc32/sysdep.h
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@ -179,8 +179,8 @@ GOT_LABEL: ; \
#else
/* Position-dependent code does not require access to the GOT. */
# define __GLRO(rOUT, rGOT, member, offset) \
lis rOUT,(member+LOWORD)@ha; \
lwz rOUT,(member+LOWORD)@l(rOUT)
lis rOUT,(member)@ha; \
lwz rOUT,(member)@l(rOUT)
#endif /* PIC */
#endif /* __ASSEMBLER__ */