mirrors/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-11-23 17:53:37 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

PowerPC: Fix little endian enconding for mfvsrd

Browse Source 
This patch fixes the MFVSRD_R3_V1 macro that encodes 'mfvsrd  r3,vs1'
(to support old binutils) for little endian.
This commit is contained in:
Adhemerval Zanella 2014-03-31 08:00:38 -05:00
parent 47c5adebd2
commit 757d9dd5c3
6 changed files with 38 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
ChangeLog
View File

@ -1,3 +1,16 @@
2014-03-31 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
* sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S (MFVSRD_R3_V1):
Encode instruction correctly in little endian.
* sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S (MFVSRD_R3_V1):
Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S (MFVSRD_R3_V1):
Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S (MFVSRD_R3_V1):
Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S (MFVSRD_R3_V1):
Likewise.
2014-03-31 Joseph Myers <joseph@codesourcery.com>
[BZ #9894]

5
sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S
View File

@ -17,9 +17,14 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
/* int [r3] __finite ([fp1] x) */

5
sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S
View File

@ -17,9 +17,14 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
/* int [r3] __isinf([fp1] x) */

5
sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S
View File

@ -17,9 +17,14 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
/* int [r3] __isnan([f1] x) */

5
sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S
View File

@ -17,9 +17,14 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
/* long long int[r3] __llrint (double x[fp1]) */
ENTRY (__llrint)

5
sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S
View File

@ -17,9 +17,14 @@
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <endian.h>
#include <math_ldbl_opt.h>
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define MFVSRD_R3_V1 .byte 0x66,0x00,0x23,0x7c /* mfvsrd r3,vs1 */
#else
#define MFVSRD_R3_V1 .byte 0x7c,0x23,0x00,0x66 /* mfvsrd r3,vs1 */
#endif
/* long long [r3] llround (float x [fp1]) */