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AArch64: Add vector logp1 alias for log1p

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This enables vectorisation of C23 logp1, which is an alias for log1p.
There are no new tests or ulp entries because the new symbols are simply
aliases.

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
This commit is contained in:
Joe Ramsay 2024-09-19 17:34:02 +01:00 committed by Wilco Dijkstra
parent 4524670545
commit 751a5502be
10 changed files with 42 additions and 1 deletions
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11
bits/libm-simd-decl-stubs.h
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@ -253,6 +253,17 @@
#define __DECL_SIMD_log1pf64x
#define __DECL_SIMD_log1pf128x
#define __DECL_SIMD_logp1
#define __DECL_SIMD_logp1f
#define __DECL_SIMD_logp1l
#define __DECL_SIMD_logp1f16
#define __DECL_SIMD_logp1f32
#define __DECL_SIMD_logp1f64
#define __DECL_SIMD_logp1f128
#define __DECL_SIMD_logp1f32x
#define __DECL_SIMD_logp1f64x
#define __DECL_SIMD_logp1f128x
#define __DECL_SIMD_atanh
#define __DECL_SIMD_atanhf
#define __DECL_SIMD_atanhl

2
math/bits/mathcalls.h
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@ -126,7 +126,7 @@ __MATHCALL (log2p1,, (_Mdouble_ __x));
__MATHCALL (log10p1,, (_Mdouble_ __x));
/* Return log(1 + X). */
__MATHCALL (logp1,, (_Mdouble_ __x));
__MATHCALL_VEC (logp1,, (_Mdouble_ __x));
#endif
#if defined __USE_XOPEN_EXTENDED || defined __USE_ISOC99

7
sysdeps/aarch64/fpu/Versions
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@ -135,4 +135,11 @@ libmvec {
_ZGVsMxv_tanh;
_ZGVsMxv_tanhf;
}
GLIBC_2.41 {
_ZGVnN2v_logp1;
_ZGVnN2v_logp1f;
_ZGVnN4v_logp1f;
_ZGVsMxv_logp1;
_ZGVsMxv_logp1f;
}
}

1
sysdeps/aarch64/fpu/advsimd_f32_protos.h
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@ -36,6 +36,7 @@ libmvec_hidden_proto (V_NAME_F2(hypot));
libmvec_hidden_proto (V_NAME_F1(log10));
libmvec_hidden_proto (V_NAME_F1(log1p));
libmvec_hidden_proto (V_NAME_F1(log2));
libmvec_hidden_proto (V_NAME_F1(logp1));
libmvec_hidden_proto (V_NAME_F1(log));
libmvec_hidden_proto (V_NAME_F2(pow));
libmvec_hidden_proto (V_NAME_F1(sin));

8
sysdeps/aarch64/fpu/bits/math-vector.h
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@ -113,6 +113,10 @@
# define __DECL_SIMD_log2 __DECL_SIMD_aarch64
# undef __DECL_SIMD_log2f
# define __DECL_SIMD_log2f __DECL_SIMD_aarch64
# undef __DECL_SIMD_logp1
# define __DECL_SIMD_logp1 __DECL_SIMD_aarch64
# undef __DECL_SIMD_logp1f
# define __DECL_SIMD_logp1f __DECL_SIMD_aarch64
# undef __DECL_SIMD_pow
# define __DECL_SIMD_pow __DECL_SIMD_aarch64
# undef __DECL_SIMD_powf
@ -180,6 +184,7 @@ __vpcs __f32x4_t _ZGVnN4v_logf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_log10f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_log1pf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_log2f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_logp1f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4vv_powf (__f32x4_t, __f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_sinf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_sinhf (__f32x4_t);
@ -207,6 +212,7 @@ __vpcs __f64x2_t _ZGVnN2v_log (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_log10 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_log1p (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_log2 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_logp1 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2vv_pow (__f64x2_t, __f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_sin (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_sinh (__f64x2_t);
@ -239,6 +245,7 @@ __sv_f32_t _ZGVsMxv_logf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_log10f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_log1pf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_log2f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_logp1f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxvv_powf (__sv_f32_t, __sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_sinf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_sinhf (__sv_f32_t, __sv_bool_t);
@ -266,6 +273,7 @@ __sv_f64_t _ZGVsMxv_log (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_log10 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_log1p (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_log2 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_logp1 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxvv_pow (__sv_f64_t, __sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_sin (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_sinh (__sv_f64_t, __sv_bool_t);

2
sysdeps/aarch64/fpu/log1p_advsimd.c
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@ -127,3 +127,5 @@ VPCS_ATTR float64x2_t V_NAME_D1 (log1p) (float64x2_t x)
return vfmaq_f64 (y, f2, p);
}
strong_alias (V_NAME_D1 (log1p), V_NAME_D1 (logp1))

2
sysdeps/aarch64/fpu/log1p_sve.c
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@ -116,3 +116,5 @@ svfloat64_t SV_NAME_D1 (log1p) (svfloat64_t x, svbool_t pg)
return y;
}
strong_alias (SV_NAME_D1 (log1p), SV_NAME_D1 (logp1))

3
sysdeps/aarch64/fpu/log1pf_advsimd.c
View File

@ -128,3 +128,6 @@ VPCS_ATTR float32x4_t V_NAME_F1 (log1p) (float32x4_t x)
}
libmvec_hidden_def (V_NAME_F1 (log1p))
HALF_WIDTH_ALIAS_F1 (log1p)
strong_alias (V_NAME_F1 (log1p), V_NAME_F1 (logp1))
libmvec_hidden_def (V_NAME_F1 (logp1))
HALF_WIDTH_ALIAS_F1 (logp1)

2
sysdeps/aarch64/fpu/log1pf_sve.c
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@ -98,3 +98,5 @@ svfloat32_t SV_NAME_F1 (log1p) (svfloat32_t x, svbool_t pg)
return y;
}
strong_alias (SV_NAME_F1 (log1p), SV_NAME_F1 (logp1))

5
sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
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@ -128,3 +128,8 @@ GLIBC_2.40 _ZGVsMxvv_hypot F
GLIBC_2.40 _ZGVsMxvv_hypotf F
GLIBC_2.40 _ZGVsMxvv_pow F
GLIBC_2.40 _ZGVsMxvv_powf F
GLIBC_2.41 _ZGVnN2v_logp1 F
GLIBC_2.41 _ZGVnN2v_logp1f F
GLIBC_2.41 _ZGVnN4v_logp1f F
GLIBC_2.41 _ZGVsMxv_logp1 F
GLIBC_2.41 _ZGVsMxv_logp1f F