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x86: Use VMM API in memcmp-evex-movbe.S and minor changes
The only change to the existing generated code is `tzcnt` -> `bsf` to save a byte of code size here and there. Rewriting with VMM API allows for memcmp-evex-movbe to be used with evex512 by including "x86-evex512-vecs.h" at the top. Complete check passes on x86-64.
This commit is contained in:
Noah Goldstein
parent
ca7d181b62
commit
419c832aba
@ -62,44 +62,38 @@ Latency:
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# define MEMCMP __memcmp_evex_movbe
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# endif
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# define VMOVU vmovdqu64
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# ifndef VEC_SIZE
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# include "x86-evex256-vecs.h"
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# endif
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# ifdef USE_AS_WMEMCMP
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# define VMOVU_MASK vmovdqu32
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# define CHAR_SIZE 4
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# define VPCMP vpcmpd
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# define VPCMPEQ vpcmpeqd
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# define VPTEST vptestmd
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# define USE_WIDE_CHAR
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# else
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# define VMOVU_MASK vmovdqu8
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# define CHAR_SIZE 1
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# define VPCMP vpcmpub
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# define VPCMPEQ vpcmpeqb
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# define VPTEST vptestmb
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# endif
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# include "reg-macros.h"
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE)
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# define XMM0 xmm16
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# define XMM1 xmm17
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# define XMM2 xmm18
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# define YMM0 ymm16
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# define XMM1 xmm17
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# define XMM2 xmm18
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# define YMM1 ymm17
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# define YMM2 ymm18
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# define YMM3 ymm19
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# define YMM4 ymm20
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# define YMM5 ymm21
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# define YMM6 ymm22
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/* Warning!
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wmemcmp has to use SIGNED comparison for elements.
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memcmp has to use UNSIGNED comparison for elemnts.
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*/
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.section .text.evex,"ax",@progbits
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.section SECTION(.text), "ax", @progbits
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/* Cache align memcmp entry. This allows for much more thorough
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frontend optimization. */
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ENTRY_P2ALIGN (MEMCMP, 6)
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@ -111,23 +105,40 @@ ENTRY_P2ALIGN (MEMCMP, 6)
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/* Fall through for [0, VEC_SIZE] as its the hottest. */
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ja L(more_1x_vec)
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/* Create mask for CHAR's we want to compare. This allows us to
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avoid having to include page cross logic. */
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movl $-1, %ecx
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bzhil %edx, %ecx, %ecx
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kmovd %ecx, %k2
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/* Create mask of bytes that are guranteed to be valid because
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of length (edx). Using masked movs allows us to skip checks
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for page crosses/zero size. */
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mov $-1, %VRAX
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bzhi %VRDX, %VRAX, %VRAX
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/* NB: A `jz` might be useful here. Page-faults that are
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invalidated by predicate execution (the evex mask) can be
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very slow. The expectation is this is not the norm so and
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"most" code will not regularly call 'memcmp' with length = 0
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and memory that is not wired up. */
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KMOV %VRAX, %k2
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/* Safe to load full ymm with mask. */
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VMOVU_MASK (%rsi), %YMM2{%k2}
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VPCMP $4,(%rdi), %YMM2, %k1{%k2}
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kmovd %k1, %eax
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testl %eax, %eax
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VMOVU_MASK (%rsi), %VMM(2){%k2}{z}
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/* Slightly different method for VEC_SIZE == 64 to save a bit of
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code size. This allows us to fit L(return_vec_0) entirely in
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the first cache line. */
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# if VEC_SIZE == 64
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VPCMPEQ (%rdi), %VMM(2), %k1{%k2}
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KMOV %k1, %VRCX
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sub %VRCX, %VRAX
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# else
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VPCMP $4, (%rdi), %VMM(2), %k1{%k2}
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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# endif
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jnz L(return_vec_0)
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ret
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.p2align 4
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.p2align 4,, 11
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L(return_vec_0):
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tzcntl %eax, %eax
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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movl (%rdi, %rax, CHAR_SIZE), %ecx
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xorl %edx, %edx
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@ -138,33 +149,36 @@ L(return_vec_0):
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (%rsi, %rax), %ecx
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# if VEC_SIZE == 64
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movb (%rdi, %rax), %al
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# else
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movzbl (%rdi, %rax), %eax
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# endif
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subl %ecx, %eax
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# endif
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ret
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.p2align 4
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.p2align 4,, 11
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L(more_1x_vec):
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/* From VEC to 2 * VEC. No branch when size == VEC_SIZE. */
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VMOVU (%rsi), %YMM1
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VMOVU (%rsi), %VMM(1)
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/* Use compare not equals to directly check for mismatch. */
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VPCMP $4,(%rdi), %YMM1, %k1
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kmovd %k1, %eax
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VPCMP $4, (%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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/* NB: eax must be destination register if going to
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L(return_vec_[0,2]). For L(return_vec_3) destination register
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must be ecx. */
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testl %eax, %eax
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L(return_vec_[0,2]). For L(return_vec_3) destination
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register must be ecx. */
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test %VRAX, %VRAX
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jnz L(return_vec_0)
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cmpq $(CHAR_PER_VEC * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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VMOVU VEC_SIZE(%rsi), %YMM2
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VPCMP $4, VEC_SIZE(%rdi), %YMM2, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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VMOVU VEC_SIZE(%rsi), %VMM(2)
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VPCMP $4, VEC_SIZE(%rdi), %VMM(2), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_1)
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/* Less than 4 * VEC. */
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@ -172,16 +186,16 @@ L(more_1x_vec):
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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VMOVU (VEC_SIZE * 2)(%rsi), %YMM3
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VPCMP $4,(VEC_SIZE * 2)(%rdi), %YMM3, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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VMOVU (VEC_SIZE * 2)(%rsi), %VMM(3)
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VPCMP $4, (VEC_SIZE * 2)(%rdi), %VMM(3), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_2)
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VMOVU (VEC_SIZE * 3)(%rsi), %YMM4
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VPCMP $4,(VEC_SIZE * 3)(%rdi), %YMM4, %k1
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kmovd %k1, %ecx
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testl %ecx, %ecx
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VMOVU (VEC_SIZE * 3)(%rsi), %VMM(4)
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VPCMP $4, (VEC_SIZE * 3)(%rdi), %VMM(4), %k1
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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jnz L(return_vec_3)
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/* Go to 4x VEC loop. */
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@ -192,8 +206,8 @@ L(more_1x_vec):
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branches. */
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/* Load first two VEC from s2 before adjusting addresses. */
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx, CHAR_SIZE), %YMM1
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx, CHAR_SIZE), %YMM2
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx, CHAR_SIZE), %VMM(1)
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx, CHAR_SIZE), %VMM(2)
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leaq -(4 * VEC_SIZE)(%rdi, %rdx, CHAR_SIZE), %rdi
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leaq -(4 * VEC_SIZE)(%rsi, %rdx, CHAR_SIZE), %rsi
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@ -202,56 +216,61 @@ L(more_1x_vec):
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/* vpxor will be all 0s if s1 and s2 are equal. Otherwise it
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will have some 1s. */
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vpxorq (%rdi), %YMM1, %YMM1
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vpxorq (VEC_SIZE)(%rdi), %YMM2, %YMM2
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vpxorq (%rdi), %VMM(1), %VMM(1)
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vpxorq (VEC_SIZE)(%rdi), %VMM(2), %VMM(2)
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VMOVU (VEC_SIZE * 2)(%rsi), %YMM3
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vpxorq (VEC_SIZE * 2)(%rdi), %YMM3, %YMM3
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VMOVU (VEC_SIZE * 2)(%rsi), %VMM(3)
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vpxorq (VEC_SIZE * 2)(%rdi), %VMM(3), %VMM(3)
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VMOVU (VEC_SIZE * 3)(%rsi), %YMM4
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/* Ternary logic to xor (VEC_SIZE * 3)(%rdi) with YMM4 while
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oring with YMM1. Result is stored in YMM4. */
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vpternlogd $0xde,(VEC_SIZE * 3)(%rdi), %YMM1, %YMM4
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VMOVU (VEC_SIZE * 3)(%rsi), %VMM(4)
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/* Ternary logic to xor (VEC_SIZE * 3)(%rdi) with VEC(4) while
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oring with VEC(1). Result is stored in VEC(4). */
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vpternlogd $0xde, (VEC_SIZE * 3)(%rdi), %VMM(1), %VMM(4)
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/* Or together YMM2, YMM3, and YMM4 into YMM4. */
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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/* Or together VEC(2), VEC(3), and VEC(4) into VEC(4). */
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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/* Test YMM4 against itself. Store any CHAR mismatches in k1.
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/* Test VEC(4) against itself. Store any CHAR mismatches in k1.
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*/
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VPTEST %YMM4, %YMM4, %k1
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VPTEST %VMM(4), %VMM(4), %k1
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/* k1 must go to ecx for L(return_vec_0_1_2_3). */
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kmovd %k1, %ecx
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testl %ecx, %ecx
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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jnz L(return_vec_0_1_2_3)
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/* NB: eax must be zero to reach here. */
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ret
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.p2align 4,, 8
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.p2align 4,, 9
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L(8x_end_return_vec_0_1_2_3):
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movq %rdx, %rdi
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L(8x_return_vec_0_1_2_3):
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/* L(loop_4x_vec) leaves result in `k1` for VEC_SIZE == 64. */
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# if VEC_SIZE == 64
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KMOV %k1, %VRCX
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# endif
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addq %rdi, %rsi
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L(return_vec_0_1_2_3):
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VPTEST %YMM1, %YMM1, %k0
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kmovd %k0, %eax
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testl %eax, %eax
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VPTEST %VMM(1), %VMM(1), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_0)
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VPTEST %YMM2, %YMM2, %k0
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kmovd %k0, %eax
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testl %eax, %eax
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VPTEST %VMM(2), %VMM(2), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_1)
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VPTEST %YMM3, %YMM3, %k0
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kmovd %k0, %eax
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testl %eax, %eax
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VPTEST %VMM(3), %VMM(3), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(return_vec_2)
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.p2align 4,, 2
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L(return_vec_3):
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/* bsf saves 1 byte from tzcnt. This keep L(return_vec_3) in one
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fetch block and the entire L(*return_vec_0_1_2_3) in 1 cache
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line. */
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bsfl %ecx, %ecx
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bsf %VRCX, %VRCX
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 3)(%rdi, %rcx, CHAR_SIZE), %eax
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xorl %edx, %edx
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@ -266,11 +285,11 @@ L(return_vec_3):
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ret
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.p2align 4
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.p2align 4,, 8
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L(return_vec_1):
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/* bsf saves 1 byte over tzcnt and keeps L(return_vec_1) in one
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fetch block. */
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bsfl %eax, %eax
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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movl VEC_SIZE(%rdi, %rax, CHAR_SIZE), %ecx
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xorl %edx, %edx
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@ -284,11 +303,11 @@ L(return_vec_1):
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# endif
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ret
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.p2align 4,, 10
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.p2align 4,, 7
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L(return_vec_2):
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/* bsf saves 1 byte over tzcnt and keeps L(return_vec_2) in one
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fetch block. */
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bsfl %eax, %eax
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %ecx
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xorl %edx, %edx
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@ -302,7 +321,7 @@ L(return_vec_2):
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# endif
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ret
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.p2align 4
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.p2align 4,, 8
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx, CHAR_SIZE), %rdx
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@ -316,62 +335,82 @@ L(more_8x_vec):
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.p2align 4
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L(loop_4x_vec):
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VMOVU (%rsi, %rdi), %YMM1
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vpxorq (%rdi), %YMM1, %YMM1
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VMOVU VEC_SIZE(%rsi, %rdi), %YMM2
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vpxorq VEC_SIZE(%rdi), %YMM2, %YMM2
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %YMM3
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vpxorq (VEC_SIZE * 2)(%rdi), %YMM3, %YMM3
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %YMM4
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vpternlogd $0xde,(VEC_SIZE * 3)(%rdi), %YMM1, %YMM4
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %ecx
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testl %ecx, %ecx
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VMOVU (%rsi, %rdi), %VMM(1)
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vpxorq (%rdi), %VMM(1), %VMM(1)
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VMOVU VEC_SIZE(%rsi, %rdi), %VMM(2)
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vpxorq VEC_SIZE(%rdi), %VMM(2), %VMM(2)
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %VMM(3)
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vpxorq (VEC_SIZE * 2)(%rdi), %VMM(3), %VMM(3)
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %VMM(4)
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vpternlogd $0xde, (VEC_SIZE * 3)(%rdi), %VMM(1), %VMM(4)
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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VPTEST %VMM(4), %VMM(4), %k1
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/* If VEC_SIZE == 64 just branch with KTEST. We have free port0
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space and it allows the loop to fit in 2x cache lines
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instead of 3. */
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# if VEC_SIZE == 64
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KTEST %k1, %k1
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# else
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KMOV %k1, %VRCX
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test %VRCX, %VRCX
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# endif
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jnz L(8x_return_vec_0_1_2_3)
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subq $-(VEC_SIZE * 4), %rdi
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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subq %rdx, %rdi
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/* rdi has 4 * VEC_SIZE - remaining length. */
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cmpl $(VEC_SIZE * 3), %edi
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jae L(8x_last_1x_vec)
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jge L(8x_last_1x_vec)
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/* Load regardless of branch. */
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %YMM3
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %VMM(3)
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/* Seperate logic as we can only use testb for VEC_SIZE == 64.
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*/
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# if VEC_SIZE == 64
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testb %dil, %dil
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js L(8x_last_2x_vec)
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# else
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cmpl $(VEC_SIZE * 2), %edi
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jae L(8x_last_2x_vec)
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jge L(8x_last_2x_vec)
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# endif
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vpxorq (VEC_SIZE * 2)(%rdx), %YMM3, %YMM3
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vpxorq (VEC_SIZE * 2)(%rdx), %VMM(3), %VMM(3)
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VMOVU (%rsi, %rdx), %YMM1
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vpxorq (%rdx), %YMM1, %YMM1
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VMOVU (%rsi, %rdx), %VMM(1)
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vpxorq (%rdx), %VMM(1), %VMM(1)
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VMOVU VEC_SIZE(%rsi, %rdx), %YMM2
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vpxorq VEC_SIZE(%rdx), %YMM2, %YMM2
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %YMM4
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vpternlogd $0xde,(VEC_SIZE * 3)(%rdx), %YMM1, %YMM4
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %ecx
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testl %ecx, %ecx
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VMOVU VEC_SIZE(%rsi, %rdx), %VMM(2)
|
||||
vpxorq VEC_SIZE(%rdx), %VMM(2), %VMM(2)
|
||||
VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %VMM(4)
|
||||
vpternlogd $0xde, (VEC_SIZE * 3)(%rdx), %VMM(1), %VMM(4)
|
||||
vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
|
||||
VPTEST %VMM(4), %VMM(4), %k1
|
||||
/* L(8x_end_return_vec_0_1_2_3) expects bitmask to still be in
|
||||
`k1` if VEC_SIZE == 64. */
|
||||
# if VEC_SIZE == 64
|
||||
KTEST %k1, %k1
|
||||
# else
|
||||
KMOV %k1, %VRCX
|
||||
test %VRCX, %VRCX
|
||||
# endif
|
||||
jnz L(8x_end_return_vec_0_1_2_3)
|
||||
/* NB: eax must be zero to reach here. */
|
||||
ret
|
||||
|
||||
/* Only entry is from L(more_8x_vec). */
|
||||
.p2align 4,, 10
|
||||
.p2align 4,, 6
|
||||
L(8x_last_2x_vec):
|
||||
VPCMP $4,(VEC_SIZE * 2)(%rdx), %YMM3, %k1
|
||||
kmovd %k1, %eax
|
||||
testl %eax, %eax
|
||||
VPCMP $4, (VEC_SIZE * 2)(%rdx), %VMM(3), %k1
|
||||
KMOV %k1, %VRAX
|
||||
test %VRAX, %VRAX
|
||||
jnz L(8x_return_vec_2)
|
||||
/* Naturally aligned to 16 bytes. */
|
||||
.p2align 4,, 5
|
||||
L(8x_last_1x_vec):
|
||||
VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %YMM1
|
||||
VPCMP $4,(VEC_SIZE * 3)(%rdx), %YMM1, %k1
|
||||
kmovd %k1, %eax
|
||||
testl %eax, %eax
|
||||
VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %VMM(1)
|
||||
VPCMP $4, (VEC_SIZE * 3)(%rdx), %VMM(1), %k1
|
||||
KMOV %k1, %VRAX
|
||||
test %VRAX, %VRAX
|
||||
jnz L(8x_return_vec_3)
|
||||
ret
|
||||
|
||||
@ -383,7 +422,7 @@ L(8x_last_1x_vec):
|
||||
L(8x_return_vec_2):
|
||||
subq $VEC_SIZE, %rdx
|
||||
L(8x_return_vec_3):
|
||||
bsfl %eax, %eax
|
||||
bsf %VRAX, %VRAX
|
||||
# ifdef USE_AS_WMEMCMP
|
||||
leaq (%rdx, %rax, CHAR_SIZE), %rax
|
||||
movl (VEC_SIZE * 3)(%rax), %ecx
|
||||
@ -399,32 +438,34 @@ L(8x_return_vec_3):
|
||||
# endif
|
||||
ret
|
||||
|
||||
.p2align 4,, 10
|
||||
.p2align 4,, 8
|
||||
L(last_2x_vec):
|
||||
/* Check second to last VEC. */
|
||||
VMOVU -(VEC_SIZE * 2)(%rsi, %rdx, CHAR_SIZE), %YMM1
|
||||
VPCMP $4, -(VEC_SIZE * 2)(%rdi, %rdx, CHAR_SIZE), %YMM1, %k1
|
||||
kmovd %k1, %eax
|
||||
testl %eax, %eax
|
||||
VMOVU -(VEC_SIZE * 2)(%rsi, %rdx, CHAR_SIZE), %VMM(1)
|
||||
VPCMP $4, -(VEC_SIZE * 2)(%rdi, %rdx, CHAR_SIZE), %VMM(1), %k1
|
||||
KMOV %k1, %VRAX
|
||||
test %VRAX, %VRAX
|
||||
jnz L(return_vec_1_end)
|
||||
|
||||
/* Check last VEC. */
|
||||
.p2align 4
|
||||
.p2align 4,, 8
|
||||
L(last_1x_vec):
|
||||
VMOVU -(VEC_SIZE * 1)(%rsi, %rdx, CHAR_SIZE), %YMM1
|
||||
VPCMP $4, -(VEC_SIZE * 1)(%rdi, %rdx, CHAR_SIZE), %YMM1, %k1
|
||||
kmovd %k1, %eax
|
||||
testl %eax, %eax
|
||||
VMOVU -(VEC_SIZE * 1)(%rsi, %rdx, CHAR_SIZE), %VMM(1)
|
||||
VPCMP $4, -(VEC_SIZE * 1)(%rdi, %rdx, CHAR_SIZE), %VMM(1), %k1
|
||||
KMOV %k1, %VRAX
|
||||
test %VRAX, %VRAX
|
||||
jnz L(return_vec_0_end)
|
||||
ret
|
||||
|
||||
|
||||
/* Don't align. Takes 2-fetch blocks either way and aligning
|
||||
will cause code to spill into another cacheline. */
|
||||
/* Don't fully align. Takes 2-fetch blocks either way and
|
||||
aligning will cause code to spill into another cacheline.
|
||||
*/
|
||||
.p2align 4,, 3
|
||||
L(return_vec_1_end):
|
||||
/* Use bsf to save code size. This is necessary to have
|
||||
L(one_or_less) fit in aligning bytes between. */
|
||||
bsfl %eax, %eax
|
||||
bsf %VRAX, %VRAX
|
||||
addl %edx, %eax
|
||||
# ifdef USE_AS_WMEMCMP
|
||||
movl -(VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %ecx
|
||||
@ -439,10 +480,11 @@ L(return_vec_1_end):
|
||||
# endif
|
||||
ret
|
||||
|
||||
.p2align 4,, 2
|
||||
/* Don't align. Takes 2-fetch blocks either way and aligning
|
||||
will cause code to spill into another cacheline. */
|
||||
L(return_vec_0_end):
|
||||
tzcntl %eax, %eax
|
||||
bsf %VRAX, %VRAX
|
||||
addl %edx, %eax
|
||||
# ifdef USE_AS_WMEMCMP
|
||||
movl -VEC_SIZE(%rdi, %rax, CHAR_SIZE), %ecx
|
||||
@ -456,7 +498,7 @@ L(return_vec_0_end):
|
||||
subl %ecx, %eax
|
||||
# endif
|
||||
ret
|
||||
/* 1-byte until next cache line. */
|
||||
|
||||
/* evex256: 2-byte until next cache line. evex512: 46-bytes
|
||||
until next cache line. */
|
||||
END (MEMCMP)
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user