mirror of
https://sourceware.org/git/glibc.git
synced 2024-11-24 02:03:35 +08:00
2008-10-01 Daniel Jacobowitz <dan@codesourcery.com>
* stdlib/longlong.h: Update from GCC.
This commit is contained in:
Roland McGrath
parent
19c10a478c
commit
2478446556
@ -229,6 +229,19 @@ UDItype __umulsidi3 (USItype, USItype);
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#define UDIV_TIME 100
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#endif /* __arm__ */
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#if defined(__arm__)
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/* Let gcc decide how best to implement count_leading_zeros. */
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#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
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#define COUNT_LEADING_ZEROS_0 32
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#endif
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#if defined (__CRIS__) && __CRIS_arch_version >= 3
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#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
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#if __CRIS_arch_version >= 8
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#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
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#endif
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#endif /* __CRIS__ */
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#if defined (__hppa) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
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@ -315,7 +328,7 @@ UDItype __umulsidi3 (USItype, USItype);
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#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("addl %5,%1\n\tadcl %3,%0" \
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__asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
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: "=r" ((USItype) (sh)), \
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"=&r" ((USItype) (sl)) \
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: "%0" ((USItype) (ah)), \
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@ -323,7 +336,7 @@ UDItype __umulsidi3 (USItype, USItype);
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"%1" ((USItype) (al)), \
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"g" ((USItype) (bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("subl %5,%1\n\tsbbl %3,%0" \
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__asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
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: "=r" ((USItype) (sh)), \
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"=&r" ((USItype) (sl)) \
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: "0" ((USItype) (ah)), \
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@ -331,31 +344,60 @@ UDItype __umulsidi3 (USItype, USItype);
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"1" ((USItype) (al)), \
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"g" ((USItype) (bl)))
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ("mull %3" \
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__asm__ ("mul{l} %3" \
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: "=a" ((USItype) (w0)), \
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"=d" ((USItype) (w1)) \
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: "%0" ((USItype) (u)), \
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"rm" ((USItype) (v)))
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#define udiv_qrnnd(q, r, n1, n0, dv) \
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__asm__ ("divl %4" \
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__asm__ ("div{l} %4" \
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: "=a" ((USItype) (q)), \
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"=d" ((USItype) (r)) \
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: "0" ((USItype) (n0)), \
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"1" ((USItype) (n1)), \
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"rm" ((USItype) (dv)))
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#define count_leading_zeros(count, x) \
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do { \
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USItype __cbtmp; \
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__asm__ ("bsrl %1,%0" \
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: "=r" (__cbtmp) : "rm" ((USItype) (x))); \
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(count) = __cbtmp ^ 31; \
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} while (0)
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#define count_trailing_zeros(count, x) \
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__asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
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#define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
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#define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
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#define UMUL_TIME 40
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#define UDIV_TIME 40
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#endif /* 80x86 */
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#if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
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: "=r" ((UDItype) (sh)), \
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"=&r" ((UDItype) (sl)) \
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: "%0" ((UDItype) (ah)), \
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"rme" ((UDItype) (bh)), \
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"%1" ((UDItype) (al)), \
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"rme" ((UDItype) (bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
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: "=r" ((UDItype) (sh)), \
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"=&r" ((UDItype) (sl)) \
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: "0" ((UDItype) (ah)), \
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"rme" ((UDItype) (bh)), \
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"1" ((UDItype) (al)), \
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"rme" ((UDItype) (bl)))
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ("mul{q} %3" \
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: "=a" ((UDItype) (w0)), \
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"=d" ((UDItype) (w1)) \
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: "%0" ((UDItype) (u)), \
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"rm" ((UDItype) (v)))
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#define udiv_qrnnd(q, r, n1, n0, dv) \
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__asm__ ("div{q} %4" \
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: "=a" ((UDItype) (q)), \
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"=d" ((UDItype) (r)) \
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: "0" ((UDItype) (n0)), \
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"1" ((UDItype) (n1)), \
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"rm" ((UDItype) (dv)))
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#define count_leading_zeros(count, x) ((count) = __builtin_clzl (x))
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#define count_trailing_zeros(count, x) ((count) = __builtin_ctzl (x))
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#define UMUL_TIME 40
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#define UDIV_TIME 40
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#endif /* x86_64 */
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#if defined (__i960__) && W_TYPE_SIZE == 32
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#define umul_ppmm(w1, w0, u, v) \
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({union {UDItype __ll; \
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@ -523,6 +565,11 @@ UDItype __umulsidi3 (USItype, USItype);
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__asm__ ("bfffo %1{%b2:%b2},%0" \
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: "=d" ((USItype) (count)) \
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: "od" ((USItype) (x)), "n" (0))
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/* Some ColdFire architectures have a ff1 instruction supported via
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__builtin_clz. */
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#elif defined (__mcfisaaplus__) || defined (__mcfisac__)
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#define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
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#define COUNT_LEADING_ZEROS_0 32
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#endif
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#endif /* mc68000 */
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@ -586,13 +633,18 @@ UDItype __umulsidi3 (USItype, USItype);
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#if defined (__mips__) && W_TYPE_SIZE == 32
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ("multu %2,%3" \
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: "=l" ((USItype) (w0)), \
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"=h" ((USItype) (w1)) \
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: "d" ((USItype) (u)), \
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"d" ((USItype) (v)))
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do { \
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UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
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(w1) = (USItype) (__x >> 32); \
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(w0) = (USItype) (__x); \
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} while (0)
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#define UMUL_TIME 10
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#define UDIV_TIME 100
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#if (__mips == 32 || __mips == 64) && ! __mips16
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#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
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#define COUNT_LEADING_ZEROS_0 32
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#endif
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#endif /* __mips__ */
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#if defined (__ns32000__) && W_TYPE_SIZE == 32
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@ -641,7 +693,9 @@ UDItype __umulsidi3 (USItype, USItype);
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|| defined (__powerpc__) /* gcc */ \
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|| defined (__POWERPC__) /* BEOS */ \
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|| defined (__ppc__) /* Darwin */ \
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|| defined (PPC) /* GNU/Linux, SysV */ \
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|| (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
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|| (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
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&& CPU_FAMILY == PPC) \
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) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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do { \
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@ -679,7 +733,10 @@ UDItype __umulsidi3 (USItype, USItype);
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__asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
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#define COUNT_LEADING_ZEROS_0 32
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#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
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|| defined (__ppc__) || defined (PPC)
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|| defined (__ppc__) \
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|| (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
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|| (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
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&& CPU_FAMILY == PPC)
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#define umul_ppmm(ph, pl, m0, m1) \
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do { \
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USItype __m0 = (m0), __m1 = (m1); \
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@ -828,18 +885,51 @@ UDItype __umulsidi3 (USItype, USItype);
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} while (0)
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#endif
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#if defined (__sh2__) && W_TYPE_SIZE == 32
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#if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
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#ifndef __sh1__
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ( \
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"dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
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: "=r" ((USItype)(w1)), \
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"=r" ((USItype)(w0)) \
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"dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
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: "=r<" ((USItype)(w1)), \
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"=r<" ((USItype)(w0)) \
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: "r" ((USItype)(u)), \
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"r" ((USItype)(v)) \
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: "macl", "mach")
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#define UMUL_TIME 5
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#endif
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/* This is the same algorithm as __udiv_qrnnd_c. */
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#define UDIV_NEEDS_NORMALIZATION 1
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { \
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extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
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__attribute__ ((visibility ("hidden"))); \
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/* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
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__asm__ ( \
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"mov%M4 %4,r5\n" \
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" swap.w %3,r4\n" \
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" swap.w r5,r6\n" \
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" jsr @%5\n" \
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" shll16 r6\n" \
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" swap.w r4,r4\n" \
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" jsr @%5\n" \
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" swap.w r1,%0\n" \
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" or r1,%0" \
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: "=r" (q), "=&z" (r) \
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: "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
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: "r1", "r2", "r4", "r5", "r6", "pr"); \
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} while (0)
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#define UDIV_TIME 80
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("clrt;subc %5,%1; subc %4,%0" \
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: "=r" (sh), "=r" (sl) \
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: "0" (ah), "1" (al), "r" (bh), "r" (bl))
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#endif /* __sh__ */
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#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
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#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
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#define count_leading_zeros(count, x) \
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@ -1153,6 +1243,23 @@ UDItype __umulsidi3 (USItype, USItype);
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} while (0)
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#endif /* __vax__ */
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#if defined (__xtensa__) && W_TYPE_SIZE == 32
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/* This code is not Xtensa-configuration-specific, so rely on the compiler
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to expand builtin functions depending on what configuration features
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are available. This avoids library calls when the operation can be
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performed in-line. */
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#define umul_ppmm(w1, w0, u, v) \
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do { \
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DWunion __w; \
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__w.ll = __builtin_umulsidi3 (u, v); \
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w1 = __w.s.high; \
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w0 = __w.s.low; \
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} while (0)
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#define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
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#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
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#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
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#endif /* __xtensa__ */
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#if defined (__z8000__) && W_TYPE_SIZE == 16
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
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