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Update libmvec multiarch functions for <cpu-features.h>
This patch updates libmvec multiarch functions to use the newly defined HAS_CPU_FEATURE, HAS_ARCH_FEATURE and LOAD_RTLD_GLOBAL_RO_RDX from <cpu-features.h>. * math/Makefile ($(addprefix $(objpfx), $(libm-vec-tests))): Remove $(objpfx)init-arch.o. * sysdeps/x86_64/fpu/Makefile (libmvec-support): Remove init-arch. * sysdeps/x86_64/fpu/math-tests-arch.h (avx_usable): Removed. (INIT_ARCH_EXT): Defined as empty. (CHECK_ARCH_EXT): Replace HAS_XXX with HAS_ARCH_FEATURE (XXX). * sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S: Remove __init_cpu_features call. Replace HAS_XXX with HAS_CPU_FEATURE/HAS_ARCH_FEATURE (XXX). * sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S: Likewise. * sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S: Likewise.
This commit is contained in:
H.J. Lu
parent
1aee37a22e
commit
1dfa4a94ae
48
ChangeLog
48
ChangeLog
@ -1,3 +1,51 @@
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2015-08-13 H.J. Lu <hongjiu.lu@intel.com>
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* math/Makefile ($(addprefix $(objpfx), $(libm-vec-tests))):
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Remove $(objpfx)init-arch.o.
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* sysdeps/x86_64/fpu/Makefile (libmvec-support): Remove
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init-arch.
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* sysdeps/x86_64/fpu/math-tests-arch.h (avx_usable): Removed.
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(INIT_ARCH_EXT): Defined as empty.
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(CHECK_ARCH_EXT): Replace HAS_XXX with HAS_ARCH_FEATURE (XXX).
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* sysdeps/x86_64/fpu/multiarch/svml_d_cos2_core.S: Remove
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__init_cpu_features call. Replace HAS_XXX with
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HAS_CPU_FEATURE/HAS_ARCH_FEATURE (XXX).
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* sysdeps/x86_64/fpu/multiarch/svml_d_cos4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_exp2_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_exp4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_log2_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_log4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_sin2_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_sin4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_cosf4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_cosf8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_logf4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_logf8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_sinf4_core.S: Likewise.
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* sysdeps/x86_64/fpu/multiarch/svml_s_sinf8_core.S: Likewise.
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2015-08-13 H.J. Lu <hongjiu.lu@intel.com>
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2015-08-13 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/i386/i686/fpu/multiarch/e_expf.c: Replace HAS_XXX
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* sysdeps/i386/i686/fpu/multiarch/e_expf.c: Replace HAS_XXX
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@ -263,7 +263,7 @@ $(objpfx)libieee.a: $(objpfx)ieee-math.o
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$(addprefix $(objpfx),$(filter-out $(tests-static) $(libm-vec-tests),$(tests))): $(libm)
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$(addprefix $(objpfx),$(filter-out $(tests-static) $(libm-vec-tests),$(tests))): $(libm)
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$(addprefix $(objpfx),$(tests-static)): $(objpfx)libm.a
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$(addprefix $(objpfx),$(tests-static)): $(objpfx)libm.a
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$(addprefix $(objpfx), $(libm-vec-tests)): $(objpfx)%: $(libm) $(libmvec) \
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$(addprefix $(objpfx), $(libm-vec-tests)): $(objpfx)%: $(libm) $(libmvec) \
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$(objpfx)init-arch.o $(objpfx)%-wrappers.o
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$(objpfx)%-wrappers.o
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gmp-objs = $(patsubst %,$(common-objpfx)stdlib/%.o,\
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gmp-objs = $(patsubst %,$(common-objpfx)stdlib/%.o,\
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add_n sub_n cmp addmul_1 mul_1 mul_n divmod_1 \
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add_n sub_n cmp addmul_1 mul_1 mul_n divmod_1 \
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@ -20,7 +20,7 @@ libmvec-support += svml_d_cos2_core svml_d_cos4_core_avx \
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svml_d_pow_data svml_s_powf4_core svml_s_powf8_core_avx \
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svml_d_pow_data svml_s_powf4_core svml_s_powf8_core_avx \
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svml_s_powf8_core svml_s_powf16_core svml_s_powf_data \
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svml_s_powf8_core svml_s_powf16_core svml_s_powf_data \
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svml_s_sincosf4_core svml_s_sincosf8_core_avx \
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svml_s_sincosf4_core svml_s_sincosf8_core_avx \
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svml_s_sincosf8_core svml_s_sincosf16_core init-arch
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svml_s_sincosf8_core svml_s_sincosf16_core
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endif
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endif
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# Variables for libmvec tests.
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# Variables for libmvec tests.
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@ -19,66 +19,36 @@
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#if defined REQUIRE_AVX
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#if defined REQUIRE_AVX
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# include <init-arch.h>
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# include <init-arch.h>
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/* Set to 1 if AVX supported. */
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# define INIT_ARCH_EXT
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static int avx_usable;
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# define INIT_ARCH_EXT \
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do \
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{ \
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__init_cpu_features (); \
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avx_usable = __cpu_features.feature[index_AVX_Usable] \
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& bit_AVX_Usable; \
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} \
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while (0)
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# define CHECK_ARCH_EXT \
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# define CHECK_ARCH_EXT \
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do \
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do \
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{ \
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{ \
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if (!avx_usable) return; \
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if (!HAS_ARCH_FEATURE (AVX_Usable)) return; \
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} \
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} \
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while (0)
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while (0)
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#elif defined REQUIRE_AVX2
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#elif defined REQUIRE_AVX2
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# include <init-arch.h>
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# include <init-arch.h>
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/* Set to 1 if AVX2 supported. */
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# define INIT_ARCH_EXT
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static int avx2_usable;
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# define INIT_ARCH_EXT \
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do \
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{ \
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__init_cpu_features (); \
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avx2_usable = __cpu_features.feature[index_AVX2_Usable] \
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& bit_AVX2_Usable; \
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} \
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while (0)
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# define CHECK_ARCH_EXT \
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# define CHECK_ARCH_EXT \
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do \
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do \
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{ \
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{ \
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if (!avx2_usable) return; \
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if (!HAS_ARCH_FEATURE (AVX2_Usable)) return; \
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} \
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} \
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while (0)
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while (0)
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#elif defined REQUIRE_AVX512F
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#elif defined REQUIRE_AVX512F
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# include <init-arch.h>
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# include <init-arch.h>
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/* Set to 1 if supported. */
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# define INIT_ARCH_EXT
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static int avx512f_usable;
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# define INIT_ARCH_EXT \
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do \
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{ \
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__init_cpu_features (); \
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avx512f_usable = __cpu_features.feature[index_AVX512F_Usable] \
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& bit_AVX512F_Usable; \
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} \
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while (0)
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# define CHECK_ARCH_EXT \
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# define CHECK_ARCH_EXT \
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do \
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do \
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{ \
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{ \
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if (!avx512f_usable) return; \
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if (!HAS_ARCH_FEATURE (AVX512F_Usable)) return; \
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} \
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} \
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while (0)
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while (0)
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@ -22,11 +22,9 @@
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.text
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.text
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ENTRY (_ZGVbN2v_cos)
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ENTRY (_ZGVbN2v_cos)
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.type _ZGVbN2v_cos, @gnu_indirect_function
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.type _ZGVbN2v_cos, @gnu_indirect_function
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cmpl $0, KIND_OFFSET+__cpu_features(%rip)
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LOAD_RTLD_GLOBAL_RO_RDX
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jne 1f
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leaq _ZGVbN2v_cos_sse4(%rip), %rax
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call __init_cpu_features
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HAS_CPU_FEATURE (SSE4_1)
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1: leaq _ZGVbN2v_cos_sse4(%rip), %rax
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testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
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jz 2f
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jz 2f
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ret
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ret
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2: leaq _ZGVbN2v_cos_sse2(%rip), %rax
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2: leaq _ZGVbN2v_cos_sse2(%rip), %rax
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@ -22,11 +22,9 @@
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.text
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.text
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ENTRY (_ZGVdN4v_cos)
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ENTRY (_ZGVdN4v_cos)
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.type _ZGVdN4v_cos, @gnu_indirect_function
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.type _ZGVdN4v_cos, @gnu_indirect_function
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cmpl $0, KIND_OFFSET+__cpu_features(%rip)
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LOAD_RTLD_GLOBAL_RO_RDX
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jne 1f
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leaq _ZGVdN4v_cos_avx2(%rip), %rax
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call __init_cpu_features
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HAS_ARCH_FEATURE (AVX2_Usable)
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1: leaq _ZGVdN4v_cos_avx2(%rip), %rax
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testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
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jz 2f
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jz 2f
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ret
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ret
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2: leaq _ZGVdN4v_cos_sse_wrapper(%rip), %rax
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2: leaq _ZGVdN4v_cos_sse_wrapper(%rip), %rax
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@ -22,14 +22,12 @@
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.text
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.text
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ENTRY (_ZGVeN8v_cos)
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ENTRY (_ZGVeN8v_cos)
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.type _ZGVeN8v_cos, @gnu_indirect_function
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.type _ZGVeN8v_cos, @gnu_indirect_function
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cmpl $0, KIND_OFFSET+__cpu_features(%rip)
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LOAD_RTLD_GLOBAL_RO_RDX
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jne 1f
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call __init_cpu_features
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1: leaq _ZGVeN8v_cos_skx(%rip), %rax
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1: leaq _ZGVeN8v_cos_skx(%rip), %rax
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testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
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HAS_ARCH_FEATURE (AVX512DQ_Usable)
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jnz 2f
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jnz 2f
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leaq _ZGVeN8v_cos_knl(%rip), %rax
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leaq _ZGVeN8v_cos_knl(%rip), %rax
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testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
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HAS_ARCH_FEATURE (AVX512F_Usable)
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jnz 2f
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jnz 2f
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leaq _ZGVeN8v_cos_avx2_wrapper(%rip), %rax
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leaq _ZGVeN8v_cos_avx2_wrapper(%rip), %rax
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2: ret
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2: ret
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.text
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.text
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ENTRY (_ZGVbN2v_exp)
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ENTRY (_ZGVbN2v_exp)
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.type _ZGVbN2v_exp, @gnu_indirect_function
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.type _ZGVbN2v_exp, @gnu_indirect_function
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cmpl $0, KIND_OFFSET+__cpu_features(%rip)
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LOAD_RTLD_GLOBAL_RO_RDX
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jne 1f
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leaq _ZGVbN2v_exp_sse4(%rip), %rax
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call __init_cpu_features
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HAS_CPU_FEATURE (SSE4_1)
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1: leaq _ZGVbN2v_exp_sse4(%rip), %rax
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testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
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jz 2f
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jz 2f
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ret
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ret
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2: leaq _ZGVbN2v_exp_sse2(%rip), %rax
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2: leaq _ZGVbN2v_exp_sse2(%rip), %rax
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.text
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.text
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ENTRY (_ZGVdN4v_exp)
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ENTRY (_ZGVdN4v_exp)
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.type _ZGVdN4v_exp, @gnu_indirect_function
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.type _ZGVdN4v_exp, @gnu_indirect_function
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cmpl $0, KIND_OFFSET+__cpu_features(%rip)
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LOAD_RTLD_GLOBAL_RO_RDX
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jne 1f
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leaq _ZGVdN4v_exp_avx2(%rip), %rax
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call __init_cpu_features
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HAS_ARCH_FEATURE (AVX2_Usable)
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1: leaq _ZGVdN4v_exp_avx2(%rip), %rax
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testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
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jz 2f
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jz 2f
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ret
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ret
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2: leaq _ZGVdN4v_exp_sse_wrapper(%rip), %rax
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2: leaq _ZGVdN4v_exp_sse_wrapper(%rip), %rax
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|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN8v_exp)
|
ENTRY (_ZGVeN8v_exp)
|
||||||
.type _ZGVeN8v_exp, @gnu_indirect_function
|
.type _ZGVeN8v_exp, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN8v_exp_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN8v_exp_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8v_exp_knl(%rip), %rax
|
leaq _ZGVeN8v_exp_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8v_exp_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN8v_exp_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN2v_log)
|
ENTRY (_ZGVbN2v_log)
|
||||||
.type _ZGVbN2v_log, @gnu_indirect_function
|
.type _ZGVbN2v_log, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN2v_log_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN2v_log_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN2v_log_sse2(%rip), %rax
|
2: leaq _ZGVbN2v_log_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN4v_log)
|
ENTRY (_ZGVdN4v_log)
|
||||||
.type _ZGVdN4v_log, @gnu_indirect_function
|
.type _ZGVdN4v_log, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN4v_log_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN4v_log_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN4v_log_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN4v_log_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN8v_log)
|
ENTRY (_ZGVeN8v_log)
|
||||||
.type _ZGVeN8v_log, @gnu_indirect_function
|
.type _ZGVeN8v_log, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN8v_log_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN8v_log_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8v_log_knl(%rip), %rax
|
leaq _ZGVeN8v_log_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8v_log_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN8v_log_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN2vv_pow)
|
ENTRY (_ZGVbN2vv_pow)
|
||||||
.type _ZGVbN2vv_pow, @gnu_indirect_function
|
.type _ZGVbN2vv_pow, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN2vv_pow_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN2vv_pow_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN2vv_pow_sse2(%rip), %rax
|
2: leaq _ZGVbN2vv_pow_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN4vv_pow)
|
ENTRY (_ZGVdN4vv_pow)
|
||||||
.type _ZGVdN4vv_pow, @gnu_indirect_function
|
.type _ZGVdN4vv_pow, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN4vv_pow_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN4vv_pow_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN4vv_pow_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN4vv_pow_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN8vv_pow)
|
ENTRY (_ZGVeN8vv_pow)
|
||||||
.type _ZGVeN8vv_pow, @gnu_indirect_function
|
.type _ZGVeN8vv_pow, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN8vv_pow_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN8vv_pow_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8vv_pow_knl(%rip), %rax
|
leaq _ZGVeN8vv_pow_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8vv_pow_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN8vv_pow_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN2v_sin)
|
ENTRY (_ZGVbN2v_sin)
|
||||||
.type _ZGVbN2v_sin, @gnu_indirect_function
|
.type _ZGVbN2v_sin, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN2v_sin_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN2v_sin_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN2v_sin_sse2(%rip), %rax
|
2: leaq _ZGVbN2v_sin_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN4v_sin)
|
ENTRY (_ZGVdN4v_sin)
|
||||||
.type _ZGVdN4v_sin, @gnu_indirect_function
|
.type _ZGVdN4v_sin, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN4v_sin_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN4v_sin_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN4v_sin_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN4v_sin_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN8v_sin)
|
ENTRY (_ZGVeN8v_sin)
|
||||||
.type _ZGVeN8v_sin, @gnu_indirect_function
|
.type _ZGVeN8v_sin, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN8v_sin_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN8v_sin_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8v_sin_knl(%rip), %rax
|
leaq _ZGVeN8v_sin_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8v_sin_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN8v_sin_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN2vvv_sincos)
|
ENTRY (_ZGVbN2vvv_sincos)
|
||||||
.type _ZGVbN2vvv_sincos, @gnu_indirect_function
|
.type _ZGVbN2vvv_sincos, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN2vvv_sincos_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN2vvv_sincos_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN2vvv_sincos_sse2(%rip), %rax
|
2: leaq _ZGVbN2vvv_sincos_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN4vvv_sincos)
|
ENTRY (_ZGVdN4vvv_sincos)
|
||||||
.type _ZGVdN4vvv_sincos, @gnu_indirect_function
|
.type _ZGVdN4vvv_sincos, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN4vvv_sincos_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN4vvv_sincos_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN4vvv_sincos_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN4vvv_sincos_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN8vvv_sincos)
|
ENTRY (_ZGVeN8vvv_sincos)
|
||||||
.type _ZGVeN8vvv_sincos, @gnu_indirect_function
|
.type _ZGVeN8vvv_sincos, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN8vvv_sincos_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN8vvv_sincos_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8vvv_sincos_knl(%rip), %rax
|
leaq _ZGVeN8vvv_sincos_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN8vvv_sincos_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN8vvv_sincos_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN16v_cosf)
|
ENTRY (_ZGVeN16v_cosf)
|
||||||
.type _ZGVeN16v_cosf, @gnu_indirect_function
|
.type _ZGVeN16v_cosf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN16v_cosf_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN16v_cosf_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_cosf_knl(%rip), %rax
|
leaq _ZGVeN16v_cosf_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_cosf_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN16v_cosf_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN4v_cosf)
|
ENTRY (_ZGVbN4v_cosf)
|
||||||
.type _ZGVbN4v_cosf, @gnu_indirect_function
|
.type _ZGVbN4v_cosf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN4v_cosf_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN4v_cosf_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN4v_cosf_sse2(%rip), %rax
|
2: leaq _ZGVbN4v_cosf_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN8v_cosf)
|
ENTRY (_ZGVdN8v_cosf)
|
||||||
.type _ZGVdN8v_cosf, @gnu_indirect_function
|
.type _ZGVdN8v_cosf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN8v_cosf_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN8v_cosf_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN8v_cosf_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN8v_cosf_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN16v_expf)
|
ENTRY (_ZGVeN16v_expf)
|
||||||
.type _ZGVeN16v_expf, @gnu_indirect_function
|
.type _ZGVeN16v_expf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN16v_expf_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN16v_expf_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_expf_knl(%rip), %rax
|
leaq _ZGVeN16v_expf_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_expf_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN16v_expf_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN4v_expf)
|
ENTRY (_ZGVbN4v_expf)
|
||||||
.type _ZGVbN4v_expf, @gnu_indirect_function
|
.type _ZGVbN4v_expf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN4v_expf_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN4v_expf_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN4v_expf_sse2(%rip), %rax
|
2: leaq _ZGVbN4v_expf_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN8v_expf)
|
ENTRY (_ZGVdN8v_expf)
|
||||||
.type _ZGVdN8v_expf, @gnu_indirect_function
|
.type _ZGVdN8v_expf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN8v_expf_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN8v_expf_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN8v_expf_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN8v_expf_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN16v_logf)
|
ENTRY (_ZGVeN16v_logf)
|
||||||
.type _ZGVeN16v_logf, @gnu_indirect_function
|
.type _ZGVeN16v_logf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN16v_logf_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN16v_logf_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_logf_knl(%rip), %rax
|
leaq _ZGVeN16v_logf_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_logf_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN16v_logf_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN4v_logf)
|
ENTRY (_ZGVbN4v_logf)
|
||||||
.type _ZGVbN4v_logf, @gnu_indirect_function
|
.type _ZGVbN4v_logf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN4v_logf_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN4v_logf_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN4v_logf_sse2(%rip), %rax
|
2: leaq _ZGVbN4v_logf_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN8v_logf)
|
ENTRY (_ZGVdN8v_logf)
|
||||||
.type _ZGVdN8v_logf, @gnu_indirect_function
|
.type _ZGVdN8v_logf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN8v_logf_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN8v_logf_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN8v_logf_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN8v_logf_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN16vv_powf)
|
ENTRY (_ZGVeN16vv_powf)
|
||||||
.type _ZGVeN16vv_powf, @gnu_indirect_function
|
.type _ZGVeN16vv_powf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN16vv_powf_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN16vv_powf_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16vv_powf_knl(%rip), %rax
|
leaq _ZGVeN16vv_powf_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16vv_powf_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN16vv_powf_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN4vv_powf)
|
ENTRY (_ZGVbN4vv_powf)
|
||||||
.type _ZGVbN4vv_powf, @gnu_indirect_function
|
.type _ZGVbN4vv_powf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN4vv_powf_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN4vv_powf_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN4vv_powf_sse2(%rip), %rax
|
2: leaq _ZGVbN4vv_powf_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN8vv_powf)
|
ENTRY (_ZGVdN8vv_powf)
|
||||||
.type _ZGVdN8vv_powf, @gnu_indirect_function
|
.type _ZGVdN8vv_powf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN8vv_powf_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN8vv_powf_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN8vv_powf_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN8vv_powf_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN16vvv_sincosf)
|
ENTRY (_ZGVeN16vvv_sincosf)
|
||||||
.type _ZGVeN16vvv_sincosf, @gnu_indirect_function
|
.type _ZGVeN16vvv_sincosf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN16vvv_sincosf_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN16vvv_sincosf_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16vvv_sincosf_knl(%rip), %rax
|
leaq _ZGVeN16vvv_sincosf_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16vvv_sincosf_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN16vvv_sincosf_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN4vvv_sincosf)
|
ENTRY (_ZGVbN4vvv_sincosf)
|
||||||
.type _ZGVbN4vvv_sincosf, @gnu_indirect_function
|
.type _ZGVbN4vvv_sincosf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN4vvv_sincosf_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN4vvv_sincosf_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN4vvv_sincosf_sse2(%rip), %rax
|
2: leaq _ZGVbN4vvv_sincosf_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN8vvv_sincosf)
|
ENTRY (_ZGVdN8vvv_sincosf)
|
||||||
.type _ZGVdN8vvv_sincosf, @gnu_indirect_function
|
.type _ZGVdN8vvv_sincosf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVdN8vvv_sincosf_avx2(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
1: leaq _ZGVdN8vvv_sincosf_avx2(%rip), %rax
|
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN8vvv_sincosf_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN8vvv_sincosf_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
@ -22,14 +22,12 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVeN16v_sinf)
|
ENTRY (_ZGVeN16v_sinf)
|
||||||
.type _ZGVeN16v_sinf, @gnu_indirect_function
|
.type _ZGVeN16v_sinf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVeN16v_sinf_skx(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_ARCH_FEATURE (AVX512DQ_Usable)
|
||||||
1: leaq _ZGVeN16v_sinf_skx(%rip), %rax
|
|
||||||
testl $bit_AVX512DQ_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512DQ_Usable(%rip)
|
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_sinf_knl(%rip), %rax
|
leaq _ZGVeN16v_sinf_knl(%rip), %rax
|
||||||
testl $bit_AVX512F_Usable, __cpu_features+FEATURE_OFFSET+index_AVX512F_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX512F_Usable)
|
||||||
jnz 2f
|
jnz 2f
|
||||||
leaq _ZGVeN16v_sinf_avx2_wrapper(%rip), %rax
|
leaq _ZGVeN16v_sinf_avx2_wrapper(%rip), %rax
|
||||||
2: ret
|
2: ret
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVbN4v_sinf)
|
ENTRY (_ZGVbN4v_sinf)
|
||||||
.type _ZGVbN4v_sinf, @gnu_indirect_function
|
.type _ZGVbN4v_sinf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
leaq _ZGVbN4v_sinf_sse4(%rip), %rax
|
||||||
call __init_cpu_features
|
HAS_CPU_FEATURE (SSE4_1)
|
||||||
1: leaq _ZGVbN4v_sinf_sse4(%rip), %rax
|
|
||||||
testl $bit_SSE4_1, __cpu_features+CPUID_OFFSET+index_SSE4_1(%rip)
|
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVbN4v_sinf_sse2(%rip), %rax
|
2: leaq _ZGVbN4v_sinf_sse2(%rip), %rax
|
||||||
|
|||||||
@ -22,11 +22,9 @@
|
|||||||
.text
|
.text
|
||||||
ENTRY (_ZGVdN8v_sinf)
|
ENTRY (_ZGVdN8v_sinf)
|
||||||
.type _ZGVdN8v_sinf, @gnu_indirect_function
|
.type _ZGVdN8v_sinf, @gnu_indirect_function
|
||||||
cmpl $0, KIND_OFFSET+__cpu_features(%rip)
|
LOAD_RTLD_GLOBAL_RO_RDX
|
||||||
jne 1f
|
|
||||||
call __init_cpu_features
|
|
||||||
1: leaq _ZGVdN8v_sinf_avx2(%rip), %rax
|
1: leaq _ZGVdN8v_sinf_avx2(%rip), %rax
|
||||||
testl $bit_AVX2_Usable, __cpu_features+FEATURE_OFFSET+index_AVX2_Usable(%rip)
|
HAS_ARCH_FEATURE (AVX2_Usable)
|
||||||
jz 2f
|
jz 2f
|
||||||
ret
|
ret
|
||||||
2: leaq _ZGVdN8v_sinf_sse_wrapper(%rip), %rax
|
2: leaq _ZGVdN8v_sinf_sse_wrapper(%rip), %rax
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user