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x86: Set Prefer_No_VZEROUPPER if AVX512ER is available
AVX512ER won't be implemented in any Xeon processors and will be in all Xeon Phi processors. Don't check CPU model number when setting Prefer_No_VZEROUPPER for Xeon Phi. Instead, set Prefer_No_VZEROUPPER if AVX512ER is available. It works with current and future Xeon Phi and non-Xeon Phi processors. * sysdeps/x86/cpu-features.c (init_cpu_features): Set Prefer_No_VZEROUPPER if AVX512ER is available. * sysdeps/x86/cpu-features.h (bit_cpu_AVX512PF): New. (bit_cpu_AVX512ER): Likewise. (bit_cpu_AVX512CD): Likewise. (bit_cpu_AVX512BW): Likewise. (bit_cpu_AVX512VL): Likewise. (index_cpu_AVX512PF): Likewise. (index_cpu_AVX512ER): Likewise. (index_cpu_AVX512CD): Likewise. (index_cpu_AVX512BW): Likewise. (index_cpu_AVX512VL): Likewise. (reg_AVX512PF): Likewise. (reg_AVX512ER): Likewise. (reg_AVX512CD): Likewise. (reg_AVX512BW): Likewise. (reg_AVX512VL): Likewise.
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ChangeLog
21
ChangeLog
@ -1,3 +1,24 @@
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2017-04-18 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/x86/cpu-features.c (init_cpu_features): Set
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Prefer_No_VZEROUPPER if AVX512ER is available.
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* sysdeps/x86/cpu-features.h
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(bit_cpu_AVX512PF): New.
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(bit_cpu_AVX512ER): Likewise.
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(bit_cpu_AVX512CD): Likewise.
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(bit_cpu_AVX512BW): Likewise.
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(bit_cpu_AVX512VL): Likewise.
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(index_cpu_AVX512PF): Likewise.
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(index_cpu_AVX512ER): Likewise.
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(index_cpu_AVX512CD): Likewise.
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(index_cpu_AVX512BW): Likewise.
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(index_cpu_AVX512VL): Likewise.
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(reg_AVX512PF): Likewise.
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(reg_AVX512ER): Likewise.
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(reg_AVX512CD): Likewise.
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(reg_AVX512BW): Likewise.
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(reg_AVX512VL): Likewise.
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2017-04-18 Florian Weimer <fweimer@redhat.com>
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* elf/dl-misc.c (_dl_sysdep_read_whole_file): Assume that
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@ -138,8 +138,6 @@ init_cpu_features (struct cpu_features *cpu_features)
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case 0x57:
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/* Knights Landing. Enable Silvermont optimizations. */
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cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
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|= bit_arch_Prefer_No_VZEROUPPER;
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case 0x5c:
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case 0x5f:
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@ -225,6 +223,12 @@ init_cpu_features (struct cpu_features *cpu_features)
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cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
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|= bit_arch_AVX_Fast_Unaligned_Load;
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/* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
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if AVX512ER is available. */
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if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
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cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
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|= bit_arch_Prefer_No_VZEROUPPER;
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/* To avoid SSE transition penalty, use _dl_runtime_resolve_slow.
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If XGETBV suports ECX == 1, use _dl_runtime_resolve_opt. */
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cpu_features->feature[index_arch_Use_dl_runtime_resolve_slow]
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@ -63,6 +63,11 @@
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#define bit_cpu_AVX2 (1 << 5)
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#define bit_cpu_AVX512F (1 << 16)
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#define bit_cpu_AVX512DQ (1 << 17)
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#define bit_cpu_AVX512PF (1 << 26)
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#define bit_cpu_AVX512ER (1 << 27)
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#define bit_cpu_AVX512CD (1 << 28)
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#define bit_cpu_AVX512BW (1 << 30)
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#define bit_cpu_AVX512VL (1u << 31)
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/* XCR0 Feature flags. */
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#define bit_XMM_state (1 << 1)
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@ -239,6 +244,11 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define index_cpu_AVX2 COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512F COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512PF COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512ER COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512CD COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512BW COMMON_CPUID_INDEX_7
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# define index_cpu_AVX512VL COMMON_CPUID_INDEX_7
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# define index_cpu_ERMS COMMON_CPUID_INDEX_7
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# define index_cpu_RTM COMMON_CPUID_INDEX_7
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# define index_cpu_FMA COMMON_CPUID_INDEX_1
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@ -258,6 +268,11 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define reg_AVX2 ebx
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# define reg_AVX512F ebx
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# define reg_AVX512DQ ebx
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# define reg_AVX512PF ebx
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# define reg_AVX512ER ebx
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# define reg_AVX512CD ebx
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# define reg_AVX512BW ebx
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# define reg_AVX512VL ebx
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# define reg_ERMS ebx
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# define reg_RTM ebx
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# define reg_FMA ecx
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