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Under extreme register pressure, compiler can use FP <--> int moves as a cheap alternate to spilling to memory. This was seen with SPEC2017 FP benchmark 507.cactu: ML_BSSN_Advect.cc:ML_BSSN_Advect_Body() | fmv.d.x fa5,s9 # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1 | .LVL325: | ld s9,184(sp) # _12469, %sfp | ... | .LVL339: | fmv.x.d s4,fa5 # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1 | The FMV instructions could be costlier (than stack spill) on certain micro-architectures, thus this needs to be a per-cpu tunable (default being to inhibit on all existing RV cpus). Testsuite run with new test reports 10 failures without the fix corresponding to the build variations of pr105666.c | === gcc Summary === | | # of expected passes 123318 (+10) | # of unexpected failures 34 (-10) | # of unexpected successes 4 | # of expected failures 780 | # of unresolved testcases 4 | # of unsupported tests 2796 gcc/ChangeLog: * config/riscv/riscv.cc: (struct riscv_tune_param): Add fmv_cost. (rocket_tune_info): Add default fmv_cost 8. (sifive_7_tune_info): Ditto. (thead_c906_tune_info): Ditto. (optimize_size_tune_info): Ditto. (riscv_register_move_cost): Use fmv_cost for int<->fp moves. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr105666.c: New test. Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> |
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