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9b7917b34f
As hinted out in the BZ, we were missing a left shift in the constant synthesis in the case where the upper 32 bits can be synthesized using a shNadd of the low 32 bits. This adjusts the synthesis to add the missing left shift and adjusts the cost to account for the additional instruction. Regression tested on riscv64-elf in my tester. Waiting for the pre-commit tester before moving forward. PR target/117690 gcc/ * config/riscv/riscv.cc (riscv_build_integer): Add missing left shift when using shNadd to derive upper 32 bits from lower 32 bits. gcc/testsuite * gcc.target/riscv/pr117690.c: New test. * gcc.target/riscv/synthesis-13.c: Adjust expected output. |
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