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When making patch to replace TARGET_P8_VECTOR, I noticed for *eqv<BOOL_128:mode>3_internal1 unlike the other logical operations, we only exploited the vsx version. I think it is an oversight, this patch is to consider veqv as well. gcc/ChangeLog: * config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand. |
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