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321 lines
6.2 KiB
ArmAsm
321 lines
6.2 KiB
ArmAsm
/* Copyright (C) 2006-2020 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the
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Free Software Foundation; either version 3, or (at your option) any
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later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Moderately Space-optimized libgcc routines for the Renesas SH /
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STMicroelectronics ST40 CPUs.
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Contributed by J"orn Rennecke joern.rennecke@st.com. */
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#include "lib1funcs.h"
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#ifdef L_udivsi3_i4i
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/* 88 bytes; sh4-200 cycle counts:
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divisor >= 2G: 11 cycles
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dividend < 2G: 48 cycles
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dividend >= 2G: divisor != 1: 54 cycles
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dividend >= 2G, divisor == 1: 22 cycles */
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#if defined (__SH_FPU_DOUBLE__) || defined (__SH4_SINGLE_ONLY__)
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!! args in r4 and r5, result in r0, clobber r1
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.global GLOBAL(udivsi3_i4i)
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FUNC(GLOBAL(udivsi3_i4i))
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GLOBAL(udivsi3_i4i):
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mova L1,r0
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cmp/pz r5
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sts fpscr,r1
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lds.l @r0+,fpscr
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sts.l fpul,@-r15
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bf LOCAL(huge_divisor)
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mov.l r1,@-r15
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lds r4,fpul
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cmp/pz r4
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#ifdef FMOVD_WORKS
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fmov.d dr0,@-r15
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float fpul,dr0
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fmov.d dr2,@-r15
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bt LOCAL(dividend_adjusted)
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mov #1,r1
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fmov.d @r0,dr2
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cmp/eq r1,r5
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bt LOCAL(div_by_1)
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fadd dr2,dr0
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LOCAL(dividend_adjusted):
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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LOCAL(div_by_1):
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fmov.d @r15+,dr2
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ftrc dr0,fpul
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fmov.d @r15+,dr0
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#else /* !FMOVD_WORKS */
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fmov.s DR01,@-r15
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mov #1,r1
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fmov.s DR00,@-r15
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float fpul,dr0
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fmov.s DR21,@-r15
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bt/s LOCAL(dividend_adjusted)
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fmov.s DR20,@-r15
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cmp/eq r1,r5
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bt LOCAL(div_by_1)
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fmov.s @r0+,DR20
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fmov.s @r0,DR21
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fadd dr2,dr0
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LOCAL(dividend_adjusted):
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lds r5,fpul
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float fpul,dr2
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fdiv dr2,dr0
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LOCAL(div_by_1):
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fmov.s @r15+,DR20
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fmov.s @r15+,DR21
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ftrc dr0,fpul
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fmov.s @r15+,DR00
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fmov.s @r15+,DR01
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#endif /* !FMOVD_WORKS */
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lds.l @r15+,fpscr
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sts fpul,r0
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rts
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lds.l @r15+,fpul
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#ifdef FMOVD_WORKS
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.p2align 3 ! make double below 8 byte aligned.
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#endif
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LOCAL(huge_divisor):
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lds r1,fpscr
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add #4,r15
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cmp/hs r5,r4
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rts
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movt r0
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.p2align 2
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L1:
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#ifndef FMOVD_WORKS
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.long 0x80000
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#else
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.long 0x180000
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#endif
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.double 4294967296
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ENDFUNC(GLOBAL(udivsi3_i4i))
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#elif !defined (__sh1__) /* !__SH_FPU_DOUBLE__ */
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#if 0
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/* With 36 bytes, the following would probably be the most compact
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implementation, but with 139 cycles on an sh4-200, it is extremely slow. */
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GLOBAL(udivsi3_i4i):
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mov.l r2,@-r15
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mov #0,r1
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div0u
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mov r1,r2
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mov.l r3,@-r15
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mov r1,r3
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sett
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mov r4,r0
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LOCAL(loop):
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rotcr r2
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;
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bt/s LOCAL(end)
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cmp/gt r2,r3
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rotcl r0
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bra LOCAL(loop)
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div1 r5,r1
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LOCAL(end):
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rotcl r0
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mov.l @r15+,r3
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rts
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mov.l @r15+,r2
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#endif /* 0 */
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/* Size: 186 bytes jointly for udivsi3_i4i and sdivsi3_i4i
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sh4-200 run times:
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udiv small divisor: 55 cycles
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udiv large divisor: 52 cycles
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sdiv small divisor, positive result: 59 cycles
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sdiv large divisor, positive result: 56 cycles
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sdiv small divisor, negative result: 65 cycles (*)
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sdiv large divisor, negative result: 62 cycles (*)
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(*): r2 is restored in the rts delay slot and has a lingering latency
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of two more cycles. */
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.balign 4
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.global GLOBAL(udivsi3_i4i)
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FUNC(GLOBAL(udivsi3_i4i))
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FUNC(GLOBAL(sdivsi3_i4i))
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GLOBAL(udivsi3_i4i):
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sts pr,r1
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mov.l r4,@-r15
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extu.w r5,r0
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cmp/eq r5,r0
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swap.w r4,r0
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shlr16 r4
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bf/s LOCAL(large_divisor)
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div0u
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mov.l r5,@-r15
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shll16 r5
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LOCAL(sdiv_small_divisor):
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div1 r5,r4
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bsr LOCAL(div6)
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div1 r5,r4
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div1 r5,r4
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bsr LOCAL(div6)
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div1 r5,r4
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xtrct r4,r0
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xtrct r0,r4
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bsr LOCAL(div7)
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swap.w r4,r4
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div1 r5,r4
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bsr LOCAL(div7)
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div1 r5,r4
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xtrct r4,r0
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mov.l @r15+,r5
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swap.w r0,r0
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mov.l @r15+,r4
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jmp @r1
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rotcl r0
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LOCAL(div7):
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div1 r5,r4
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LOCAL(div6):
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div1 r5,r4; div1 r5,r4; div1 r5,r4
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div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
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LOCAL(divx3):
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rotcl r0
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div1 r5,r4
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rotcl r0
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div1 r5,r4
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rotcl r0
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rts
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div1 r5,r4
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LOCAL(large_divisor):
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mov.l r5,@-r15
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LOCAL(sdiv_large_divisor):
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xor r4,r0
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.rept 4
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rotcl r0
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bsr LOCAL(divx3)
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div1 r5,r4
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.endr
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mov.l @r15+,r5
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mov.l @r15+,r4
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jmp @r1
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rotcl r0
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ENDFUNC(GLOBAL(udivsi3_i4i))
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.global GLOBAL(sdivsi3_i4i)
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GLOBAL(sdivsi3_i4i):
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mov.l r4,@-r15
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cmp/pz r5
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mov.l r5,@-r15
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bt/s LOCAL(pos_divisor)
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cmp/pz r4
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neg r5,r5
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extu.w r5,r0
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bt/s LOCAL(neg_result)
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cmp/eq r5,r0
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neg r4,r4
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LOCAL(pos_result):
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swap.w r4,r0
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bra LOCAL(sdiv_check_divisor)
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sts pr,r1
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LOCAL(pos_divisor):
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extu.w r5,r0
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bt/s LOCAL(pos_result)
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cmp/eq r5,r0
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neg r4,r4
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LOCAL(neg_result):
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mova LOCAL(negate_result),r0
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;
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mov r0,r1
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swap.w r4,r0
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lds r2,macl
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sts pr,r2
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LOCAL(sdiv_check_divisor):
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shlr16 r4
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bf/s LOCAL(sdiv_large_divisor)
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div0u
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bra LOCAL(sdiv_small_divisor)
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shll16 r5
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.balign 4
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LOCAL(negate_result):
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neg r0,r0
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jmp @r2
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sts macl,r2
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ENDFUNC(GLOBAL(sdivsi3_i4i))
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#endif /* !__SH_FPU_DOUBLE__ */
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#endif /* L_udivsi3_i4i */
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#ifdef L_sdivsi3_i4i
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#if defined (__SH_FPU_DOUBLE__) || defined (__SH4_SINGLE_ONLY__)
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/* 48 bytes, 45 cycles on sh4-200 */
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!! args in r4 and r5, result in r0, clobber r1
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.global GLOBAL(sdivsi3_i4i)
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FUNC(GLOBAL(sdivsi3_i4i))
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GLOBAL(sdivsi3_i4i):
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sts.l fpscr,@-r15
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sts fpul,r1
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mova L1,r0
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lds.l @r0+,fpscr
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lds r4,fpul
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#ifdef FMOVD_WORKS
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fmov.d dr0,@-r15
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float fpul,dr0
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lds r5,fpul
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fmov.d dr2,@-r15
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#else
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fmov.s DR01,@-r15
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fmov.s DR00,@-r15
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float fpul,dr0
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lds r5,fpul
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fmov.s DR21,@-r15
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fmov.s DR20,@-r15
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#endif
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float fpul,dr2
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fdiv dr2,dr0
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#ifdef FMOVD_WORKS
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fmov.d @r15+,dr2
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#else
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fmov.s @r15+,DR20
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fmov.s @r15+,DR21
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#endif
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ftrc dr0,fpul
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#ifdef FMOVD_WORKS
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fmov.d @r15+,dr0
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#else
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fmov.s @r15+,DR00
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fmov.s @r15+,DR01
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#endif
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lds.l @r15+,fpscr
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sts fpul,r0
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rts
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lds r1,fpul
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.p2align 2
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L1:
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#ifndef FMOVD_WORKS
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.long 0x80000
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#else
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.long 0x180000
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#endif
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ENDFUNC(GLOBAL(sdivsi3_i4i))
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#endif /* __SH_FPU_DOUBLE__ */
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#endif /* L_sdivsi3_i4i */
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