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-
41344d6077
SARIF output: fix schema URL [§3.13.3, PR116603]
David Malcolm
2024-09-09 19:38:11 -0400 -
0f26f4f769
analyzer: handle <error.h> at -O0 [PR115724]
2024-07-04 14:44:51 -0400 -
d5d62a3849
testsuite: use check-jsonschema for validating .sarif files [PR109360]
2024-06-25 20:26:21 -0400 -
bf01dcd117
testsuite: check that generated .sarif files validate against the SARIF schema [PR109360]
2024-06-21 08:46:14 -0400 -
07485ccd31
diagnostics: fixes to SARIF output [PR109360]
2024-06-21 08:46:13 -0400 -
54504e8c70
regenerate-opt-urls.py: fix transposed values for "vax" and "v850"
2024-05-28 15:47:38 -0400 -
156051d083
testsuite: fix analyzer C++ failures on Solaris [PR111475]
2024-05-03 09:05:29 -0400 -
0b52da2198
omp-cp: Add callback redirection, not working yet
Josef Melcr
2024-11-20 12:02:30 +0100 -
d54a66c1d8
Work in progress for refactoring simd intrinsic
devel/existing-fp8
Saurabh Jha
2024-11-19 22:38:51 +0000 -
0e3e2cc03e
[PATCH] PR modula2/115276 bugfix libgm2 wraptime.InitTM returns NIL
Gaius Mulley
2024-11-20 09:22:53 +0000 -
83c51f98e7
[PATCH] modula2: simplify xref usage in documentation, remove external ref to gm2.
2024-11-20 08:15:45 +0000 -
a6ee740ff3
[PATCH] modula2: fix xref fourth parameter in documentation, change from gm2 to m2
2024-11-20 08:14:10 +0000 -
84198cba68
Daily bump.
GCC Administrator
2024-11-20 00:23:31 +0000 -
4899656a8b
Daily bump.
2024-11-20 00:22:28 +0000 -
61ce58768a
Daily bump.
2024-11-20 00:21:13 +0000 -
9a23dff4f8
[PATCH] modula2: use groups in the type resolver of the bootstrap tool mc
2024-11-20 00:17:23 +0000 -
b1d2c143e8
[PATCH] modula2: Pass --destdir for dir index during install of m2.info.
2024-11-19 22:28:04 +0000 -
aefb471444
[PATCH] PR modula2/115164 initial test code highlighting the problem
2024-11-19 19:33:18 +0000 -
399065ea44
[PATCH] PR modula2/115057 TextIO.ReadRestLine raises an exception when buffer is exceeded
2024-11-19 18:30:10 +0000 -
540c0c7c42
i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]
Uros Bizjak
2024-11-18 22:38:46 +0100 -
724dbdad0d
i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]
2024-11-18 22:38:46 +0100 -
112d184348
[PATCH] PR modula2/115003 exporting a symbol to outer scope with a name clash causes ICE
2024-11-19 15:32:02 +0000 -
acf93643ab
fortran: Evaluate once BACK argument of MINLOC/MAXLOC with DIM [PR90608]
Mikael Morin
2024-10-03 15:57:50 +0200 -
efd0ef174b
fortran: Check for empty MINLOC/MAXLOC ARRAY along DIM only
2023-11-18 20:54:20 +0100 -
98f7802c63
fortran: Inline non-character MINLOC/MAXLOC with DIM [PR90608]
2024-08-08 12:23:16 +0200 -
7daaeb2119
fortran: Check MASK directly instead of its scalarization chain
2024-09-12 16:56:39 +0200 -
855dfebae6
fortran: Inline MINLOC/MAXLOC with DIM and scalar MASK [PR90608]
2024-08-08 13:44:16 +0200 -
068259e9f3
fortran: Inline unmasked integral MINLOC/MAXLOC with DIM [PR90608]
2023-11-17 19:04:19 +0100 -
29fcac59d6
fortran: Add tests covering inline MINLOC/MAXLOC with DIM [PR90608]
2023-11-16 10:00:26 +0100 -
57df36f036
fold-const: Fix BIT_INSERT_EXPR folding for BYTES_BIG_ENDIAN [PR116997]
Andre Vieira
2024-10-14 16:24:07 +0100 -
4d27dd15c4
Daily bump.
2024-11-19 00:22:54 +0000 -
4453b2cfef
Daily bump.
2024-11-19 00:22:08 +0000 -
2bca9b85f4
Daily bump.
2024-11-19 00:20:33 +0000 -
fee4616138
i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]
2024-11-18 22:38:46 +0100 -
a2725b4ed6
AVR: target/117659 - Fix wrong code for u24 << 16.
Georg-Johann Lay
2024-11-18 18:12:38 +0100 -
3c15b26d5f
AVR: target/117659 - Fix wrong code for u24 << 16.
2024-11-18 18:12:38 +0100 -
3cb7ac6f02
AVR: target/117659 - Fix wrong code for u24 << 16.
2024-11-18 18:12:38 +0100 -
b51b45eaf7
fold-const: Fix BIT_INSERT_EXPR folding for BYTES_BIG_ENDIAN [PR116997]
2024-10-14 16:24:07 +0100 -
71cce6c774
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
Michael Meissner
2024-11-18 00:04:34 -0500 -
4b4bcc55e5
Revert changes
2024-11-17 23:39:05 -0500 -
0a1ae1fb13
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 23:27:17 -0500 -
72607d8e90
Revert changes
2024-11-17 23:26:02 -0500 -
a5a5aa1275
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 23:16:46 -0500 -
8b4bb54e6c
i386: Zero extend 32-bit address to 64-bit with option -mx32 -maddress-mode=long. [PR 117418]
Hu, Lin1
2024-11-06 15:42:13 +0800 -
1c6b11ccc2
Revert changes
2024-11-17 20:26:48 -0500 -
2759b96d46
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 20:20:26 -0500 -
f3059f83d4
Revert changes
2024-11-17 20:16:20 -0500 -
a6699802d5
Daily bump.
2024-11-18 00:25:08 +0000 -
8ebc82fff9
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 19:22:29 -0500 -
c6646b5a74
Daily bump.
2024-11-18 00:21:34 +0000 -
061572fae4
Revert changes
2024-11-17 19:20:27 -0500 -
83e485e74b
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 19:11:17 -0500 -
76887290ab
Revert changes
2024-11-17 19:05:35 -0500 -
3666adaf05
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 18:41:44 -0500 -
316942ce50
Revert changes
2024-11-17 18:40:50 -0500 -
b5906edb9d
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 18:13:28 -0500 -
d57549e16e
Revert changes
2024-11-17 18:11:53 -0500 -
8480aca690
Update ChangeLog.*
2024-11-17 17:16:30 -0500 -
f6b4501037
PR target/108958 -- use mtvsrdd to zero extend GPR DImode to VSX TImode
2024-11-17 17:15:08 -0500 -
f084bd952d
Update ChangeLog.*
2024-11-16 20:35:01 -0500 -
110f2975eb
Update ChangeLog.*
2024-11-16 20:11:35 -0500 -
fe0da4dce7
Daily bump.
2024-11-17 00:32:22 +0000 -
4d9c98ad9f
Daily bump.
2024-11-17 00:28:48 +0000 -
8618eb7060
Merge commit 'refs/users/meissner/heads/work186-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work186-vpair
2024-11-16 19:26:46 -0500 -
a8d1d7ef87
Update ChangeLog.*
2024-11-16 02:26:23 -0500 -
10de735a24
Vector pair support.
2024-11-16 02:23:52 -0500 -
f2b9cb858b
Add ChangeLog.vpair and update REVISION.
2024-11-14 12:08:51 -0500 -
557449775b
Merge commit 'refs/users/meissner/heads/work186-test' of git+ssh://gcc.gnu.org/git/gcc into me/work186-test
2024-11-16 19:25:24 -0500 -
bb265cb6fd
Add ChangeLog.test and update REVISION.
2024-11-14 12:12:40 -0500 -
d0bb7a14ff
Daily bump.
2024-11-17 00:24:56 +0000 -
62082e9dac
Merge commit 'refs/users/meissner/heads/work186-sha' of git+ssh://gcc.gnu.org/git/gcc into me/work186-sha
2024-11-16 19:23:26 -0500 -
234501f7cd
Update ChangeLog.*
2024-11-16 02:21:29 -0500 -
9a76736714
Add potential p-future XVRLD and XVRLDI instructions.
2024-11-16 02:18:12 -0500 -
fc52575389
PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
2024-11-16 02:17:05 -0500 -
4981d1eb63
Revert changes
2024-11-16 02:15:46 -0500 -
7ca461bf9c
Add potential p-future XVRLD and XVRLDI instructions.
2024-11-16 02:14:19 -0500 -
c3bb48609f
PR target/117251: Add PowerPC XXEVAL support to speed up SHA3 calculations
2024-11-16 02:10:28 -0500 -
ed2a7bd9c9
Add ChangeLog.sha and update REVISION.
2024-11-14 12:11:43 -0500 -
d6d6f5f3e7
Merge commit 'refs/users/meissner/heads/work186-libs' of git+ssh://gcc.gnu.org/git/gcc into me/work186-libs
2024-11-16 19:21:57 -0500 -
28d7d2f58a
Add ChangeLog.libs and update REVISION.
2024-11-14 12:10:52 -0500 -
cd14719407
Merge commit 'refs/users/meissner/heads/work186-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work186-dmf
2024-11-16 19:18:44 -0500 -
4f30bca742
Update ChangeLog.*
2024-11-16 01:57:04 -0500 -
c9dcd4796b
RFC2655-Add saturating subtract built-ins.
2024-11-16 01:50:54 -0500 -
44ecaba7a3
RFC2656-Support load/store vector with right length.
2024-11-16 01:43:32 -0500 -
dab4366f82
RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
2024-11-16 01:35:43 -0500 -
c25bdd1e56
RFC2653-Add dense math test for new instruction names.
2024-11-16 01:29:27 -0500 -
5959d9cf80
RFC2653-PowerPC: Switch to dense math names for all MMA operations.
2024-11-16 01:27:55 -0500 -
3c40e73d86
RFC2653-Add support for dense math registers.
2024-11-16 01:26:00 -0500 -
68acb44d2f
RFC2653-Add wD constraint.
2024-11-16 01:20:12 -0500 -
e31291c086
Add ChangeLog.dmf and update REVISION.
2024-11-14 12:07:59 -0500 -
be4c4f00f7
Merge commit 'refs/users/meissner/heads/work186-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work186-bugs
2024-11-16 19:17:16 -0500 -
81f1e1e306
Update ChangeLog.*
2024-11-16 02:32:52 -0500 -
8996f75cb6
Add power9 and power10 float to logical optimizations.
2024-11-16 02:30:10 -0500 -
97bec89d0c
PR 99293: Optimize splat of a V2DF/V2DI extract with constant element
2024-11-16 02:28:44 -0500 -
c57154a52f
Add ChangeLog.bugs and update REVISION.
2024-11-14 12:09:49 -0500 -
b822fba141
Update ChangeLog.*
2024-11-16 19:11:51 -0500 -
e481a8ed36
Vector pair test only runs in 64-bits
2024-11-16 19:10:21 -0500 -
dac2236d12
AVR: target/117500 - Use output_operand_lossage in avr_print_operand.
2024-11-09 12:40:48 +0100 -
74bfca7360
AVR: target/117500 - Use output_operand_lossage in avr_print_operand.
2024-11-09 12:40:48 +0100 -
05e2c6dca9
Update ChangeLog.*
2024-11-16 02:32:52 -0500