gcc/
* config/mips/mips.c (mips_rewrite_small_data_1): Take the context
as a parameter instead of the containing MEM. Iterate over all
subrtxes. Don't return a value.
(mips_rewrite_small_data): Update call accordingly.
From-SVN: r216708
gcc/
* config/mips/mips.c: Include rtl-iter.h.
(mips_small_data_pattern_1): Take an rtx rather than an rtx pointer.
Take the context as a parameter instead of the containing MEM.
Iterate over all subrtxes.
(mips_small_data_pattern_p): Update call accordingly.
From-SVN: r216707
gcc/
* config/mep/mep.c (mep_store_find_set): Take a const_rtx and
return a bool. Replace "void *" with specific type. Iterate
over all subrtxes.
(mep_store_data_bypass_1): Update calls accordingly.
From-SVN: r216705
gcc/
* config/mep/mep.c: Include rtl-iter.h.
(global_reg_mentioned_p_1): Take a const_rtx and return a bool.
(xtensa_tls_referenced_p): Return a bool. Use FOR_EACH_SUBRTX.
From-SVN: r216704
gcc/
* config/sh/sh-protos.h (shmedia_cleanup_truncate): Take an
rtx as argument and return the number of changes.
* config/sh/sh.c: Include rtl-iter.h.
(shmedia_cleanup_truncate): Take an rtx as argument and iterate
over all subrtxes. Return the number of changes made.
* config/sh/sh.md: Update caller accordingly.
From-SVN: r216701
PR rtl-optimization/63615
* simplify-rtx.c (simplify_plus_minus): Set "canonicalized" on
decomposing PLUS or MINUS if operands are not placed adjacent
in the "ops" array.
From-SVN: r216689
rs6000_hard_regno_nregs_internal allows SPE vectors in single
registers satisfying SPE_SIMD_REGNO_P (i.e. register numbers 0 to
31). However, the corresponding test for e500 double treats all
registers as being able to store a 64-bit value, rather than just
those GPRs.
Logically this inconsistency is wrong; in addition, it causes problems
unwinding from signal handlers. linux-unwind.h uses
ARG_POINTER_REGNUM as a place to store the return address from a
signal handler, but this logic in rs6000_hard_regno_nregs_internal
results in that being considered an 8-byte register, resulting in
assertion failures.
(<https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02625.html> first
needs to be applied for unwinding to work in general on e500.) This
patch makes rs6000_hard_regno_nregs_internal handle the e500 double
case consistently with SPE vectors.
Tested with no regressions with cross to powerpc-linux-gnuspe (given
the aforementioned patch applied). Failures of signal handling
unwinding tests such as gcc.dg/cleanup-{8,9,10,11}.c are fixed by this
patch.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Do
not allow e500 double in registers not satisyfing
SPE_SIMD_REGNO_P.
From-SVN: r216688
Continuing the cleanups of libgcc soft-fp configuration for
powerpc*-*-linux* in preparation for implementing
TARGET_ATOMIC_ASSIGN_EXPAND_FENV for soft-float and e500, this patch
optimizes the choice of which functions to build for the 32-bit
classic hard-float and soft-float cases. (e500 will be dealt with in
a separate patch which will need to add new features to t-hardfp and
t-softfp; this patch keeps the status quo for e500.)
For hard-float, while the functions in question are part of the libgcc
ABI there is no need for them to contain software floating point code:
no newly built code should use them, and if anything does use them
it's most efficient (space and speed) for them to pass straight
through to floating-point hardware instructions; this case is made to
use t-hardfp to achieve that. For soft-float, direct use of soft-fp
functions for operations involving DImode or unsigned integers is more
efficient than using the libgcc2.c versions of those operations to
convert to operations on other types (which then end up calling
soft-fp functions for those other types, possibly more than once);
this case is thus stopped from using t-softfp-excl. (A future patch
will stop the e500 cases from using t-softfp-excl as well.)
Tested with no regressions for crosses to powerpc-linux-gnu (soft
float and classic hard float); also checked that the same set of
symbols and versions is exported from shared libgcc before and after
the patch.
* configure.ac (ppc_fp_type): Set variable on powerpc*-*-linux*.
* configure: Regenerate.
* config.host (powerpc*-*-linux*): Use $ppc_fp_type to determine
additions to tmake_file. Use t-hardfp-sfdf and t-hardfp instead
of soft-fp for 32-bit classic hard float. Do not use
t-softfp-excl for soft float.
From-SVN: r216687
gcc:
* ginclude/stdbool.h: Do not define bool, true or false in C++11.
libstdc++-v3:
* testsuite/18_support/headers/cstdbool/macros.cc: New.
From-SVN: r216679
2014-10-24 Charles Baylis <charles.baylis@linaro.org>
* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rewrite using builtins,
update uses to use new macro arguments.
(__LD3_LANE_FUNC): Likewise.
(__LD4_LANE_FUNC): Likewise.
From-SVN: r216672
2014-10-24 Paolo Carlini <paolo.carlini@oracle.com>
* include/bits/atomic_base.h: Avoid including <stdbool.h>.
* include/std/atomic: When __cplusplus < 201103L skip the rest of
the header.
* testsuite/29_atomics/headers/atomic/std_c++0x_neg.cc: Adjust.
From-SVN: r216667
