Commit Graph

182724 Commits

Author SHA1 Message Date
GCC Administrator
872373360d Daily bump. 2021-01-10 00:16:20 +00:00
Iain Buclaw
7da827c99c d: Synchronize testsuite with upstream dmd
Adds TEST_OUTPUT directives and reduces the verbosity of many tests.

Reviewed-on: https://github.com/dlang/dmd/pull/12112

gcc/d/ChangeLog:

	* dmd/MERGE: Merge upstream dmd cb1106ad5.
2021-01-09 23:59:30 +01:00
Iain Buclaw
7a103daef7 d: Support deprecated, @disable, and user-defined attributes on enum members
Reviewed-on: https://github.com/dlang/dmd/pull/12108

gcc/d/ChangeLog:

	* dmd/MERGE: Merge upstream dmd 9bba772fa.
2021-01-09 23:45:46 +01:00
Iain Buclaw
acae7b21bc d: Implement expression-based contract syntax
Expression-based contract syntax has been added.  Contracts that consist
of a single assertion can now be written more succinctly and multiple
`in` or `out` contracts can be specified for the same function.

Reviewed-on: https://github.com/dlang/dmd/pull/12106

gcc/d/ChangeLog:

	* dmd/MERGE: Merge upstream dmd e598f69c0.
2021-01-09 23:45:46 +01:00
Maciej W. Rozycki
f2a5346244 VAX/testsuite: Remove notsi comparison elimination regressions
Remove fallout from commit 0bd675183d ("match.pd: Add ~(X - Y) -> ~X
+ Y simplification [PR96685]") and paper over the regression caused as
it is not the matter of the test cases affected.

Previously assembly like this:

	.text
	.align 1
.globl eq_notsi
	.type	eq_notsi, @function
eq_notsi:
	.word 0	# 35	[c=0]  procedure_entry_mask
	subl2 $4,%sp	# 46	[c=32]  *addsi3
	mcoml 4(%ap),%r0	# 32	[c=16]  *one_cmplsi2_ccz
	jeql .L1		# 34	[c=26]  *branch_ccz
	addl2 $2,%r0	# 31	[c=32]  *addsi3
.L1:
	ret		# 40	[c=0]  return
	.size	eq_notsi, .-eq_notsi

was produced.  Now this:

	.text
	.align 1
.globl eq_notsi
	.type	eq_notsi, @function
eq_notsi:
	.word 0	# 36	[c=0]  procedure_entry_mask
	subl2 $4,%sp	# 48	[c=32]  *addsi3
	movl 4(%ap),%r0	# 33	[c=16]  *movsi_2
	cmpl %r0,$-1	# 34	[c=8]  *cmpsi_ccz/1
	jeql .L3		# 35	[c=26]  *branch_ccz
	subl3 %r0,$1,%r0	# 32	[c=32]  *subsi3/1
	ret		# 27	[c=0]  return
.L3:
	clrl %r0		# 31	[c=2]  *movsi_2
	ret		# 41	[c=0]  return
	.size	eq_notsi, .-eq_notsi

is, which cannot work with post-reload comparison elimination, due to
the comparison against -1 rather than 0.

Use subtraction from a constant then rather than addition as the former
operation is not transformed, removing these regressions:

FAIL: gcc.target/vax/cmpelim-eq-notsi.c   -O1   scan-rtl-dump-times cmpelim "deleting insn with uid" 1
FAIL: gcc.target/vax/cmpelim-eq-notsi.c   -O1   scan-assembler-not \t(bit|cmpz?|tst).
FAIL: gcc.target/vax/cmpelim-eq-notsi.c   -O1   scan-assembler one_cmplsi[^ ]*_ccz(/[0-9]+)?\n
FAIL: gcc.target/vax/cmpelim-lt-notsi.c   -O1   scan-rtl-dump-times cmpelim "deleting insn with uid" 1
FAIL: gcc.target/vax/cmpelim-lt-notsi.c   -O1   scan-assembler-not \t(bit|cmpz?|tst).
FAIL: gcc.target/vax/cmpelim-lt-notsi.c   -O1   scan-assembler one_cmplsi[^ ]*_ccn(/[0-9]+)?\n

and likewise across some of the other the optimization levels verified.

The LE variant appears unaffected as the new transformation produces
slightly different although still suboptimal code:

	.text
	.align 1
.globl le_notsi
	.type	le_notsi, @function
le_notsi:
	.word 0	# 27	[c=0]  procedure_entry_mask
	subl2 $4,%sp	# 34	[c=32]  *addsi3
	movl 4(%ap),%r1	# 23	[c=16]  *movsi_2
	mcoml %r1,%r0	# 24	[c=8]  *one_cmplsi2_ccnz
	jleq .L1		# 26	[c=26]  *branch_ccnz
	subl3 %r1,$1,%r0	# 22	[c=32]  *subsi3/1
.L1:
	ret		# 32	[c=0]  return
	.size	le_notsi, .-le_notsi

but update the test case too, for consistency with the other two.

	gcc/testsuite/
	* gcc.target/vax/cmpelim-eq-notsi.c: Use subtraction from a
	constant then rather than addition.
	* gcc.target/vax/cmpelim-le-notsi.c: Likewise.
	* gcc.target/vax/cmpelim-lt-notsi.c: Likewise.
2021-01-09 16:30:51 +00:00
Maciej W. Rozycki
7f5c4d23db VAX: Remove a duplicate `cc' mode attribute
Remove the `cc' mode attribute that duplicates the implicitly defined
`mode' attribute.  No change to semantics.

	gcc/
	* config/vax/vax.md (cc): Remove mode attribute.
	(subst_<cc>, subst_f<cc>): Rename to...
	(subst_<mode>, subst_f<VAXccnz:mode>): ... these respectively.
	(*cbranch<VAXint:mode>4_<VAXcc:mode>): Update for `cc' removal.
	(*cbranch<VAXfp:mode>4_<VAXccnz:mode>): Likewise.
	(*branch_<mode>, *branch_<mode>_reversed): Likewise.
2021-01-09 16:30:50 +00:00
Maciej W. Rozycki
c38bbf5eed VAX: Use a mode with `const_double_zero' expressions
For predictable semantics propagate the mode from operands referred by
the FP substitution to the `const_double_zero' expressions used with the
associated condition code calculation.  Use an iterator to make copies
of the FP substitution across the FP modes supported as the substitution
now has to match the mode of the operands.

	gcc/
	* config/vax/vax.md (subst_f<cc>): Add mode to operands and
	`const_double_zero'.
2021-01-09 16:30:25 +00:00
Maciej W. Rozycki
be7e807242 PDP11: Use a mode with `const_double_zero' expressions
For predictable semantics propagate the mode from operands referred by
FP substitutions to the `const_double_zero' expressions used with the
associated condition code calculation, resulting in the following update
to insn-emit.c code produced for the `pdp11-aout' target (with machine
description line numbering change noise removed):

@@ -1514,7 +1514,7 @@
 	gen_rtx_COMPARE (CCmode,
 	gen_rtx_ABS (DFmode,
 	operand1),
-	CONST_DOUBLE_ATOF ("0", VOIDmode))),
+	CONST_DOUBLE_ATOF ("0", DFmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_ABS (DFmode,
 	copy_rtx (operand1)))));
@@ -1555,7 +1555,7 @@
 	gen_rtx_COMPARE (CCmode,
 	gen_rtx_NEG (DFmode,
 	operand1),
-	CONST_DOUBLE_ATOF ("0", VOIDmode))),
+	CONST_DOUBLE_ATOF ("0", DFmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_NEG (DFmode,
 	copy_rtx (operand1)))));
@@ -1790,7 +1790,7 @@
 	gen_rtx_MULT (DFmode,
 	operand1,
 	operand2),
-	CONST_DOUBLE_ATOF ("0", VOIDmode))),
+	CONST_DOUBLE_ATOF ("0", DFmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_MULT (DFmode,
 	copy_rtx (operand1),
@@ -1942,7 +1942,7 @@
 	gen_rtx_DIV (DFmode,
 	operand1,
 	operand2),
-	CONST_DOUBLE_ATOF ("0", VOIDmode))),
+	CONST_DOUBLE_ATOF ("0", DFmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_DIV (DFmode,
 	copy_rtx (operand1),

Provide a new iterator to provide copies of FP substitutions across the
FP modes supported as the substitutions now need to match the mode of
the operands.

	gcc/
	* config/pdp11/pdp11.md (PDPfp): New mode iterator.
	(fcc_cc, fcc_ccnz): Use it.  Add mode to `const_double_zero' and
	operands.
2021-01-09 15:50:27 +00:00
Maciej W. Rozycki
859be2e44a RTL: Update `const_double_zero' handling for mode and callable insns
Handle machine mode specification with `const_double_zero' and handle
the rtx with callable code produced from named insns.  Complementing
commit 20ab43b5ca ("RTL: Add `const_double_zero' syntactic rtx") and
removing a commit c60d0736df ("PDP11: Use `const_double_zero' to
express double zero constant") build regression observed with the
`pdp11-aout' target:

genemit: Internal error: abort in gen_exp, at genemit.c:202
make[2]: *** [Makefile:2427: s-emit] Error 1

where a:

(const_double 0 [0] 0 [0] 0 [0] 0 [0])

rtx coming from:

(parallel [
        (set (reg:CC 16)
            (compare:CC (abs:DF (match_operand:DF 1 ("general_operand") ("0,0")))
                (const_double 0 [0] 0 [0] 0 [0] 0 [0])))
        (set (match_operand:DF 0 ("nonimmediate_operand") ("=fR,Q"))
            (abs:DF (match_dup 1)))
    ])

and ultimately `(const_double_zero)' referred in a named RTL insn cannot
be interpreted.  Handle the rtx then by supplying the constant 0 double
operand requested, resulting in the following update to insn-emit.c code
produced for the `pdp11-aout' target, relative to before the triggering
commit:

@@ -1514,7 +1514,7 @@ gen_absdf2_cc (rtx operand0 ATTRIBUTE_UN
 	gen_rtx_COMPARE (CCmode,
 	gen_rtx_ABS (DFmode,
 	operand1),
-	const0_rtx)),
+	CONST_DOUBLE_ATOF ("0", VOIDmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_ABS (DFmode,
 	copy_rtx (operand1)))));
@@ -1555,7 +1555,7 @@ gen_negdf2_cc (rtx operand0 ATTRIBUTE_UN
 	gen_rtx_COMPARE (CCmode,
 	gen_rtx_NEG (DFmode,
 	operand1),
-	const0_rtx)),
+	CONST_DOUBLE_ATOF ("0", VOIDmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_NEG (DFmode,
 	copy_rtx (operand1)))));
@@ -1790,7 +1790,7 @@ gen_muldf3_cc (rtx operand0 ATTRIBUTE_UN
 	gen_rtx_MULT (DFmode,
 	operand1,
 	operand2),
-	const0_rtx)),
+	CONST_DOUBLE_ATOF ("0", VOIDmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_MULT (DFmode,
 	copy_rtx (operand1),
@@ -1942,7 +1942,7 @@ gen_divdf3_cc (rtx operand0 ATTRIBUTE_UN
 	gen_rtx_DIV (DFmode,
 	operand1,
 	operand2),
-	const0_rtx)),
+	CONST_DOUBLE_ATOF ("0", VOIDmode))),
 		gen_rtx_SET (operand0,
 	gen_rtx_DIV (DFmode,
 	copy_rtx (operand1),

This does not (yet) remove VOIDmode CONST_DOUBLE use, as it is up to
individual machine descriptions to choose.

	gcc/
	* genemit.c (gen_exp) <CONST_DOUBLE>: Handle `const_double_zero'
	rtx.
	* read-rtl.c (rtx_reader::read_rtx_code): Handle machine mode
	with `const_double_zero'.
	* doc/rtl.texi (Constant Expression Types): Document it.
2021-01-09 15:46:02 +00:00
Jakub Jelinek
991656092f tree-cfg: Allow enum types as result of POINTER_DIFF_EXPR [PR98556]
As conversions between signed integers and signed enums with the same
precision are useless in GIMPLE, it seems strange that we require that
POINTER_DIFF_EXPR result must be INTEGER_TYPE.

If we really wanted to require that, we'd need to change the gimplifier
to ensure that, which it isn't the case on the following testcase.
What is going on during the gimplification is that when we have the
(enum T) (p - q) cast, it is stripped through
      /* Strip away as many useless type conversions as possible
         at the toplevel.  */
      STRIP_USELESS_TYPE_CONVERSION (*expr_p);
and when the MODIFY_EXPR is gimplified, the *to_p has enum T type,
while *from_p has intptr_t type and as there is no conversion in between,
we just create GIMPLE_ASSIGN from that.

2021-01-09  Jakub Jelinek  <jakub@redhat.com>

	PR c++/98556
	* tree-cfg.c (verify_gimple_assign_binary): Allow lhs of
	POINTER_DIFF_EXPR to be any integral type.

	* c-c++-common/pr98556.c: New test.
2021-01-09 10:49:38 +01:00
Jakub Jelinek
16dae48e9c vregs: Fix up instantiate_virtual_regs_in_insn for asm goto with outputs [PR98603]
If an asm insn fails constraint checking during vregs, it is just deleted.
We don't delete asm goto though because of the edges to the labels, so
instantiate_virtual_regs_in_insn would just remove the inputs and their
constraints, the pattern etc.
This worked fine when asm goto couldn't have output operands, but causes
ICEs later on when it has more than one output (and furthermore doesn't
really remove the problematic outputs).  The problem is that
for multiple outputs we have a PARALLEL with multiple ASM_OPERANDS, but
those must use the same ASM_OPERANDS_INPUT_VEC etc., but the code was
adjusting just one.

The following patch turns invalid asm goto into a bare
asm goto ("" : : : : lab, lab2, lab3);
i.e. no inputs/outputs/clobbers, just the labels.

2021-01-09  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/98603
	* function.c (instantiate_virtual_regs_in_insn): For asm goto
	with impossible constraints, drop all SETs, CLOBBERs, drop PARALLEL
	if any, set ASM_OPERANDS mode to VOIDmode and change
	ASM_OPERANDS_OUTPUT_CONSTRAINT and ASM_OPERANDS_OUTPUT_IDX.

	* gcc.target/i386/pr98603.c: New test.
	* gcc.target/aarch64/pr98603.c: New test.
2021-01-09 10:48:20 +01:00
Alexandre Oliva
57450da2fe final: accept markers at line 0
Back when I introduced debug markers, I seem to have been under the
impression that location line 0 would only ever occur for unknown and
builtin locations.

Though line 0 never comes up in normal processing of source files, and
debug info formats often cannot represent them, I suppose there's no
need to preemptively discard them during final.


for  gcc/ChangeLog

	PR debug/97714
	* final.c (notice_source_line): Narrow down the condition to
	skip a line-0 marker.

for  gcc/testsuite/ChangeLog

	PR debug/97714
	* gcc.dg/debug/pr97714.c: New.
2021-01-09 00:09:02 -03:00
GCC Administrator
bf5cbb9edf Daily bump. 2021-01-09 00:16:22 +00:00
Sergei Trofimovich
0b874e0ffd ipa-modref: avoid linebreak split in debug print
* ipa-modref.c (merge_call_side_effects): Fix
	linebreak split by reordering two print calls.
2021-01-08 21:25:29 +00:00
Ilya Leoshkevich
0e47d6c808 IBM Z: Fix constraints in vpdi patterns
The destination register is only partially overwritten, so + should be
used instead of =.

gcc/ChangeLog:

2021-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>

	* config/s390/vector.md (*tf_to_fprx2_0): Rename from
	"*mov_tf_to_fprx2_0" for consistency, fix constraint.
	(*tf_to_fprx2_1): Rename from "*mov_tf_to_fprx2_1" for
	consistency, fix constraint.
2021-01-08 18:15:47 +01:00
H.J. Lu
745d04e796 x86-64: Require lp64 for PR target/98482 tests
Require lp64 for PR target/98482 tests since -mcmodel=large is isn't
supported for x32.

	PR target/98482
	* gcc.target/i386/pr98482-1.c: Require lp64.
	* gcc.target/i386/pr98482-2.c: Likewise.
2021-01-08 08:47:06 -08:00
Ilya Leoshkevich
f47df2af31 IBM Z: Introduce __LONG_DOUBLE_VX__ macro
Give end users the opportunity to find out whether long doubles are
stored in floating-point register pairs or in vector registers, so that
they could fine-tune their asm statements.

gcc/ChangeLog:

2020-12-14  Ilya Leoshkevich  <iii@linux.ibm.com>

	* config/s390/s390-c.c (s390_def_or_undef_macro): Accept
	callables instead of mask values.
	(struct target_flag_set_p): New predicate.
	(s390_cpu_cpp_builtins_internal): Define or undefine
	__LONG_DOUBLE_VX__ macro.

2020-12-14  Ilya Leoshkevich  <iii@linux.ibm.com>

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/long-double-vx-macro-off-on.c: New test.
	* gcc.target/s390/vector/long-double-vx-macro-on-off.c: New test.
2021-01-08 17:43:24 +01:00
Olivier Hainque
98546324c7 Tweak dg-prune-output regex for out-of-build-tree contexts
libstdc++-v3/

	* testsuite/20_util/bind/ref_neg.cc: Tweak the
	dg-prune-output regex for out-of-build-tree contexts.
2021-01-08 16:23:23 +00:00
Patrick Palka
bb1f0b50ab c++: ICE with constexpr call that returns a PMF [PR98551]
We shouldn't do replace_result_decl after evaluating a call that returns
a PMF because PMF temporaries aren't wrapped in a TARGET_EXPR (and so we
can't trust ctx->object), and PMF initializers can't be self-referential
anyway, so replace_result_decl would always be a no-op.

To that end, this patch changes the relevant AGGREGATE_TYPE_P test to
CLASS_TYPE_P, which should rule out PMFs (as well as arrays, which we
can't return and therefore won't see here).  This fixes an ICE from the
sanity check in replace_result_decl in the below testcase during
constexpr evaluation of the call f() in the initializer g(f()).

gcc/cp/ChangeLog:

	PR c++/98551
	* constexpr.c (cxx_eval_call_expression): Check CLASS_TYPE_P
	instead of AGGREGATE_TYPE_P before calling replace_result_decl.

gcc/testsuite/ChangeLog:

	PR c++/98551
	* g++.dg/cpp0x/constexpr-pmf2.C: New test.
2021-01-08 10:11:25 -05:00
Patrick Palka
98a1fb705e c++: Fix access checking of scoped non-static member [PR98515]
In the first testcase below, we incorrectly reject the use of the
protected non-static member A::var0 from C<int>::g() because
check_accessibility_of_qualified_id, at template parse time, determines
that the access doesn't go through 'this'.  (This happens because the
dependent base B<T> of C<T> doesn't have a binfo object, so it appears
to DERIVED_FROM_P that A is not an indirect base of C<T>.)  From there
we create the corresponding deferred access check, which we then
perform at instantiation time and which (expectedly) fails.

The problem ultimately seems to be that we can't in general determine
whether a use of a scoped non-static member goes through 'this' until
instantiation time, as the second testcase below illustrates.  So this
patch makes check_accessibility_of_qualified_id punt in such situations
to avoid creating a bogus deferred access check.

gcc/cp/ChangeLog:

	PR c++/98515
	* semantics.c (check_accessibility_of_qualified_id): Punt if
	we're checking access of a scoped non-static member inside a
	class template.

gcc/testsuite/ChangeLog:

	PR c++/98515
	* g++.dg/template/access32.C: New test.
	* g++.dg/template/access33.C: New test.
2021-01-08 10:02:04 -05:00
H.J. Lu
76be18f442 x86-64: Use R10 and R11 for profiling large model with PIC
For NO_PROFILE_COUNTERS targets, R11 is a scratch register.  We can use
R10 and R11 to call mcount in large model with PIC.

gcc/

	PR target/98482
	* config/i386/i386.c (x86_function_profiler): Use R10 and R11
	to call mcount in large model with PIC for NO_PROFILE_COUNTERS
	targets.

gcc/testsuite/

	PR target/98482
	* gcc.target/i386/pr98482-2.c: Updated.
2021-01-08 06:46:04 -08:00
Richard Biener
77a375a3eb reset the SCEV htab after FRE in loop pipeline
When running FRE in the loop pipeline (as part of the conditionally
scheduled scalar cleanups) we have to reset the SCEV hashtable as
otherwise we can end up with stale entries and all sorts of problems.

Catched by my out-of-tree verifier for this problem.

2021-01-08  Richard Biener  <rguenther@suse.de>

	* tree-ssa-sccvn.c (pass_fre::execute): Reset the SCEV hash table.
2021-01-08 15:10:40 +01:00
Richard Biener
b407f233d7 fix vectorizer memleaks
This plugs two memleaks in the vectorizer.

2021-01-08  Richard Biener  <rguenther@suse.de>

	* tree-vect-slp.c (scalar_stmts_to_slp_tree_map_t): Fix.
	(vect_build_slp_tree): On cache hit release the matched
	scalar stmts vector.
	* tree-vect-stmts.c (vectorizable_store): Properly free
	vec_oprnds before possibly gathering them again.
2021-01-08 14:23:44 +01:00
Richard Biener
bdcde15045 tree-optimization/98544 - more permute optimization fixes
Permute nodes are not transparent to the permute of their children.
Instead we have to materialize child permutes always and in future
may treat permute nodes as the source of arbitrary permutes as
we can permute the lane permutation vector at will (as the target
supports in the end).

2021-01-08  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/98544
	* tree-vect-slp.c (vect_optimize_slp): Always materialize
	permutes at a permute node.

	* gcc.dg/vect/bb-slp-pr98544.c: New testcase.
2021-01-08 14:08:10 +01:00
H.J. Lu
1b885264a4 x86-64: Use R10 for profiling large model
R10 is caller-saved.  Although it can be used as a static chain register,
it is preserved when calling mcount for nested functions.  Use R10 as a
scratch register to call mcount in large model.

gcc/

	PR target/98482
	* config/i386/i386.c (x86_function_profiler): Use R10 to call
	mcount in large model.  Sorry for large model with PIC.

gcc/testsuite/

	PR target/98482
	* gcc.target/i386/pr98482-1.c: New test.
	* gcc.target/i386/pr98482-1.c: Likewise.
2021-01-08 04:51:57 -08:00
Jakub Jelinek
8f1cb70d7c i386: Fix -mcmodel= vs. target attribute [PR98585]
My patch to save/restore opts_set rather than essentially treating
global_options_set as a logical or whether some option has ever been
explicitly set somewhere apparently broke -mcmodel= vs. target attribute
(and as the patch shows some other options too).
The thing is, at least for options for which we ever test opts_set->x_*
or global_options_set.x_*, we need to save/restore them next to the
saving/restoring of the actual option values.
If an option has Save keyword or in case of TargetVariable, it is the
generic code that handles the saving and restoring of both the option
and corresponding opts_set flag automatically, for other variables
(TargetSave, or Target without Save) the backend needs to do that in the
target hook manually and in that case should save/restore both the option
values (the hooks mostly did that) and opts_set (they didn't).

As it seems much easier to let the automatic saving/restoring do the work
for us unless the saving/restoring of the option needs some specific magic,
the following patch is a result of grepping through the backend for
opts_set->x_ and global_options_set.x_ and for all such referenced
variables, grepping whether it is saved/restored including opts_set properly
in the generated options-save.c or not.

2021-01-08  Jakub Jelinek  <jakub@redhat.com>

	PR target/98585
	* config/i386/i386.opt (ix86_cmodel, ix86_incoming_stack_boundary_arg,
	ix86_pmode, ix86_preferred_stack_boundary_arg, ix86_regparm,
	ix86_veclibabi_type): Remove x_ prefix, use TargetVariable instead of
	TargetSave and initialize for variables with enum types.
	(mfentry, mstack-protector-guard-reg=, mstack-protector-guard-offset=,
	mstack-protector-guard-symbol=): Add Save.
	* config/i386/i386-options.c (ix86_function_specific_save,
	ix86_function_specific_restore): Don't save or restore x_ix86_cmodel,
	x_ix86_incoming_stack_boundary_arg, x_ix86_pmode,
	x_ix86_preferred_stack_boundary_arg, x_ix86_regparm,
	x_ix86_veclibabi_type.

	* gcc.target/i386/pr98585.c: New test.
2021-01-08 12:28:25 +01:00
Richard Sandiford
5fe3e6bf06 aarch64: Support unpacked CNOT on SVE
This patch adds unpacked support for unconditional and
conditional CNOT.  The type suffix has to be taken from
the element size rather than the container size.

gcc/
	* config/aarch64/aarch64-sve.md (*cnot<mode>): Extend from
	SVE_FULL_I to SVE_I.
	(*cond_cnot<mode>_2, *cond_cnot<mode>_any): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/sve/cnot_2.c: New test.
	* gcc.target/aarch64/sve/cond_cnot_4.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_4_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_5.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_5_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_6.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_6_run.c: Likewise.
2021-01-08 10:49:38 +00:00
Richard Sandiford
f3c5d1fa53 aarch64: Support conditional unpacked UXT on SVE
This patch extends the conditional UXT patterns from SVE_FULL_I
to SVE_I.  It doesn't matter in this case whether the type suffix
is taken from the element size or the container size.

gcc/
	* config/aarch64/aarch64-sve.md (*cond_uxt<mode>_2): Extend from
	SVE_FULL_I to SVE_I.
	(*cond_uxt<mode>_any): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/sve/cond_uxt_5.c: New test.
	* gcc.target/aarch64/sve/cond_uxt_5_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_6.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_6_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_7.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_7_run.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_8.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_8_run.c: Likewise.
2021-01-08 10:49:37 +00:00
Tamar Christina
07fb24a3da SVE2: Fix aarch64-sve2-acle-asm tests.
This fixes a logical inconsistency with the SVE2 ACLE tests where the SVE2 tests
are checking for SVE support in the assembler instead of SVE2.

This makes all these tests fail when the user has an SVE enabled assembler but
not an SVE2 one.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp
	(check_effective_target_aarch64_asm_sve2_ok): New.
	* g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Use it.
	* gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Likewise.
2021-01-08 10:45:23 +00:00
Kyrylo Tkachov
e811f10b61 aarch64: Reimplement most vpadal intrinsics using builtins
This patch reimplements most of the vpadal intrinsics to use RTL
builtins in the normal way.
The ones that aren't converted are the int32x2_t -> int64x1_t ones as
the RTL pattern doesn't currently handle
these modes. We don't have a V1DI mode so it would need to return a
DImode value or a V2DI one with the first lane
being the result. It's not hard to do, but it would require a bit more
refactoring so we can do it separately later.

This patch hopefully improves the status quo.

The new Vwhalf mode attribute is created because the existing Vwtype
attribute maps V8QI wrongly (for this pattern) to "8h" as the
suffix rather than "4h" as needed.

gcc/
	* config/aarch64/iterators.md (Vwhalf): New iterator.
	* config/aarch64/aarch64-simd.md (aarch64_<sur>adalp<mode>_3):
	Rename to...
	(aarch64_<sur>adalp<mode>): ... This.  Make more
	builtin-friendly.
	(<sur>sadv16qi): Adjust callsite of the above.
	* config/aarch64/aarch64-simd-builtins.def (sadalp, uadalp): New
	builtins.
	* config/aarch64/arm_neon.h (vpadal_s8): Reimplement using
	builtins.
	(vpadal_s16): Likewise.
	(vpadal_u8): Likewise.
	(vpadal_u16): Likewise.
	(vpadalq_s8): Likewise.
	(vpadalq_s16): Likewise.
	(vpadalq_s32): Likewise.
	(vpadalq_u8): Likewise.
	(vpadalq_u16): Likewise.
	(vpadalq_u32): Likewise.
2021-01-08 10:29:25 +00:00
Kyrylo Tkachov
79db5945ad aarch64: Reimplement vabd* intrinsics using builtins
This patch reimplements the vabd* intrinsics using RTL builtins.
It's fairly straightforward with new builtins + arm_neon.h changes.

gcc/
	* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>_3):
	Rename to...
	(aarch64_<su>abd<mode>): ... This.
	(<sur>sadv16qi): Adjust callsite of the above.
	* config/aarch64/aarch64-simd-builtins.def (sabd, uabd): Define
	builtins.
	* config/aarch64/arm_neon.h (vabd_s8): Reimplement using
	builtin.
	(vabd_s16): Likewise.
	(vabd_s32): Likewise.
	(vabd_u8): Likewise.
	(vabd_u16): Likewise.
	(vabd_u32): Likewise.
	(vabdq_s8): Likewise.
	(vabdq_s16): Likewise.
	(vabdq_s32): Likewise.
	(vabdq_u8): Likewise.
	(vabdq_u16): Likewise.
	(vabdq_u32): Likewise.
2021-01-08 10:29:25 +00:00
Kyrylo Tkachov
cab822d4ea aarch64: Reimplement vaba* intrinsics using builtins
This patch reimplements the vaba* arm_neon.h intrinsics using RTL
builtins that expand to proper RTL patterns
rather than using inline asm.
The implementation is fairly straightforward by defining new builtins
and using them in the header.

gcc/
	* config/aarch64/aarch64-simd-builtins.def (saba, uaba): Define
	builtins.
	* config/aarch64/arm_neon.h (vaba_s8): Implement using builtin.
	(vaba_s16): Likewise.
	(vaba_s32): Likewise.
	(vaba_u8): Likewise.
	(vaba_u16): Likewise.
	(vaba_u32): Likewise.
	(vabaq_s8): Likewise.
	(vabaq_s16): Likewise.
	(vabaq_s32): Likewise.
	(vabaq_u8): Likewise.
	(vabaq_u16): Likewise.
	(vabaq_u32): Likewise.
2021-01-08 10:29:25 +00:00
Kyrylo Tkachov
c9d25aa748 aarch64: Fix RTL patterns for UABA/SABA
Sometime ago we changed the RTL representation of the (SU)ABD
instructions in RTL to a (MINUS (MAX) (MIN)) rather than a (MINUS (ABS) (ABS))
as it is more correctly models the semantics.
We should do the same for the accumulation forms of these instructions:
UABA/SABA.

This patch does that and allows the new pattern to generate the unsigned
UABA form as well.
The new form also allows it to more easily be re-used to implement the
relevant arm_neon.h intrinsics in the future.

The testcase takes an -fno-tree-reassoc to work around a side-effect of
PR98581.

gcc/
	* config/aarch64/aarch64-simd.md (aba<mode>_3): Rename to...
	(aarch64_<su>aba<mode>): ... This.  Handle uaba as well.
	Change RTL pattern to match.

gcc/testsuite/
	* gcc.target/aarch64/usaba_1.c: New test.
2021-01-08 10:29:25 +00:00
Paul Thomas
21c1a30fc7 Fortran: Allow pointer deferred length associate selectors. [PR93794]
2021-01-05  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
	PR fortran/93794
	* trans-expr.c (gfc_conv_component_ref): Remove the condition
	that deferred character length components only be allocatable.

gcc/testsuite/
	PR fortran/93794
	* gfortran.dg/deferred_character_35.f90 : New test.
2021-01-08 10:15:22 +00:00
Paul Thomas
c231fca5de Fortran:Fix simplification of constructors with implied-do [PR98458]
2021-01-08  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
	PR fortran/98458
	* simplify.c (is_constant_array_expr): If an array constructor
	expression has elements other than constants or structures, try
	fixing the expression with gfc_reduce_init_expr. Also, if shape
	is NULL, obtain the array size and set it.

gcc/testsuite/
	PR fortran/98458
	* gfortran.dg/implied_do_3.f90 : New test.
2021-01-08 10:11:00 +00:00
Kito Cheng
01d92cfd79 Fix array-quals-1.c for RISC-V
RISC-V will put those variable on srodata rather than rodata.

gcc/testsuite/ChangeLog:

	* gcc.dg/array-quals-1.c: Allow srodata.
2021-01-08 11:14:03 +08:00
Kito Cheng
e3354b6de7 RISC-V: Implement new style of architecture extension test macros.
- This patch introduce new set of architecture extension test macros
  which is accept on riscv-c-api-doc recently.
  - https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro

- We will also mark deprecated for legacy architecture extension test macros
  in GCC 11, but still support that for 1 or 2 release cycles.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.c (riscv_current_subset_list): New.
	* config/riscv/riscv-c.c (riscv-subset.h): New.
	(INCLUDE_STRING): Define.
	(riscv_cpu_cpp_builtins): Add new style architecture extension
	test macros.
	* config/riscv/riscv-subset.h (riscv_subset_list::begin): New.
	(riscv_subset_list::end): New.
	(riscv_current_subset_list): New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/predef-10.c: New.
	* gcc.target/riscv/predef-11.c: New.
	* gcc.target/riscv/predef-12.c: New.
	* gcc.target/riscv/predef-13.c: New.
2021-01-08 11:14:02 +08:00
Kito Cheng
0b7b471011 RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h
Pre-work of new style of architecture extension test macros, we need the
list used in `config/riscv/riscv-c.c`, so those struct/class declaration
must move to header file rather than local C file.

gcc/ChangeLog

	* common/config/riscv/riscv-common.c (RISCV_DONT_CARE_VERSION):
	Move to riscv-subset.h.
	(struct riscv_subset_t): Ditto.
	(class riscv_subset_list): Ditto.
	* config/riscv/riscv-subset.h (RISCV_DONT_CARE_VERSION): Move
	from riscv-common.c.
	(struct riscv_subset_t): Ditto.
	(class riscv_subset_list): Ditto.
	* config/riscv/t-riscv ($(common_out_file)): Add file
	dependency.
2021-01-08 11:14:02 +08:00
GCC Administrator
7d187e4f6f Daily bump. 2021-01-08 00:16:23 +00:00
Jakub Jelinek
aa4db31dd2 c++: Fix up tsubst of BIT_CAST_EXPR [PR98329]
As the testcase shows, calling cp_build_bit_cast in tsubst_copy doesn't seem
to be a good idea, because tsubst_copy might not really make the operand
non-dependent, but as processing_template_decl can be 0,
type_dependent_expression_p will return false and then cp_build_bit_cast
assumes the type is non-NULL and non-dependent.
So, this patch just follows what is done e.g. for NOP_EXPR etc. and just
builds some tree in tsubst_copy, and only calls the semantics.c function
from tsubst_copy_and_build.

2021-01-07  Jakub Jelinek  <jakub@redhat.com>

	PR c++/98329
	* pt.c (tsubst_copy) <case BIT_CAST_EXPR>: Don't call
	cp_build_bit_cast here, instead just build_min a BIT_CAST_EXPR and set
	its location.
	(tsubst_copy_and_build): Handle BIT_CAST_EXPR.

	* g++.dg/cpp2a/bit-cast10.C: New test.
2021-01-07 23:00:28 +01:00
Martin Sebor
178f0afce3 PR middle-end/98578 - ICE warning on uninitialized VLA access
gcc/c-family/ChangeLog:

	PR middle-end/98578
	* c-pretty-print.c (print_mem_ref): Strip array from access type.
	Avoid assuming acces type's size is constant.  Correct condition
	guarding the printing of a parenthesis.

gcc/testsuite/ChangeLog:

	PR middle-end/98578
	* gcc.dg/plugin/gil-1.c: Adjust expected output.
	* gcc.dg/uninit-pr98578.c: New test.
2021-01-07 14:22:28 -07:00
Marek Polacek
2f359597e4 c++: Fix thinko in auto return type checking [PR98441]
This fixes a thinko in my r11-2085 patch: when I said "But only give the
!late_return_type errors when funcdecl_p, to accept e.g. auto (*fp)() = f;
in C++11" I should've done this, otherwise we give bogus errors mentioning
"function with trailing return type" when there is none.

gcc/cp/ChangeLog:

	PR c++/98441
	* decl.c (grokdeclarator): Move the !funcdecl_p check inside the
	!late_return_type block.

gcc/testsuite/ChangeLog:

	PR c++/98441
	* g++.dg/cpp0x/auto55.C: New test.
2021-01-07 16:19:29 -05:00
Jason Merrill
6c59b8a93c c++: Add TARGET_EXPR comments
Discussing the 98469 patch and class prvalues with Jakub led me to
double-check our handling of TARGET_EXPR in constexpr.c, and add a note
about why we don't strip them in parameter initialization.  And another to
clarify that we're handling an INIT_EXPR in a place we do strip them.

gcc/cp/ChangeLog:

	* constexpr.c (cxx_bind_parameters_in_call): Add comment.
	(cxx_eval_store_expression): Add comment.
2021-01-07 16:09:11 -05:00
Jason Merrill
4d65a07d54 c++: Add some conversion sanity checking.
Another change I was working on revealed that for complex numbers we were
building a ck_identity with build_conv, leading to the wrong active member
in the union being set.  Rather than add another enumeration of the
appropriate conversion codes, I factored that out.

gcc/cp/ChangeLog:

	* call.c (has_next): Factor out from...
	(next_conversion): ...here.
	(strip_standard_conversion): And here.
	(is_subseq): And here.
	(build_conv): Check it.
	(standard_conversion): Don't call build_conv
	for ck_identity.
2021-01-07 16:05:09 -05:00
Thomas Rodgers
b7c3f201be libstdc++: Add support for C++20 barriers
Adds <barrier>

libstdc++-v3/ChangeLog:

	* doc/doxygen/user.cfg.in: Add new header.
	* include/Makefile.am (std_headers): likewise.
	* include/Makefile.in: Regenerate.
	* include/precompiled/stdc++.h: Add new header.
	* include/std/barrier: New file.
	* include/std/version: Add __cpp_lib_barrier feature test macro.
	* testsuite/30_threads/barrier/1.cc: New test.
	* testsuite/30_threads/barrier/2.cc: Likewise.
	* testsuite/30_threads/barrier/arrive_and_drop.cc: Likewise.
	* testsuite/30_threads/barrier/arrive_and_wait.cc: Likewise.
	* testsuite/30_threads/barrier/arrive.cc: Likewise.
	* testsuite/30_threads/barrier/completion.cc: Likewise.
2021-01-07 12:52:37 -08:00
David Malcolm
0677759f75 analyzer: fix ICE when DECL_INITIAL is error_mark_node [PR98580]
lto-streamer-out.c's get_symbol_initial_value can return error_mark_node
rather than DECL_INITIAL as an optimization to avoid extra sections for
simple scalar values.

Add a check to the analyzer to handle such cases gracefully.

gcc/analyzer/ChangeLog:
	PR analyzer/98580
	* region.cc (decl_region::get_svalue_for_initializer): Gracefully
	handle when LTO writes out DECL_INITIAL as error_mark_node.

gcc/testsuite/ChangeLog:
	PR analyzer/98580
	* gcc.dg/analyzer/pr98580-a.c: New test.
	* gcc.dg/analyzer/pr98580-b.c: New test.
2021-01-07 15:45:29 -05:00
Ian Lance Taylor
b87ec922c4 test: add new Go tests from source repo 2021-01-07 11:02:17 -08:00
Joseph Myers
c8d2ed112e Update cpplib es.po.
* es.po: Update.
2021-01-07 17:54:39 +00:00
Patrick Palka
19f3c433cd libstdc++: Fix long double to_chars testcase [PR98384]
The testcase was failing to compile on some targets due to its use of
the non-standard functions nextupl and nextdownl.  This patch makes the
testcase instead use the C99 function nexttowardl in an equivalent way.

libstdc++-v3/ChangeLog:

	PR libstdc++/98384
	* testsuite/20_util/to_chars/long_double.cc: Use nexttowardl
	instead of the non-standard nextupl and nextdownl.
2021-01-07 12:41:14 -05:00
Paul Thomas
85fb1d7d5f Fortran: Improve resolution of associate variables. [PR93701].
2021-01-07  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
	PR fortran/93701
	* resolve.c (find_array_spec): Put static prototype for
	resolve_assoc_var before this function and call for associate
	variables.

gcc/testsuite/
	PR fortran/93701
	* gfortran.dg/associate_54.f90: New test.
	* gfortran.dg/associate_55.f90: New test.
	* gfortran.dg/associate_56.f90: New test.
2021-01-07 17:34:49 +00:00