This patch improves emitted code for the non-TARGET_LZCNT case.
As __builtin_clz* is UB on 0 argument and for !TARGET_LZCNT
CLZ_VALUE_DEFINED_AT_ZERO is 0, it is UB even at RTL time and so we
can take advantage of that and assume the result will be 0 to 31 or
0 to 63.
Given that, sign or zero extension of that result are the same and
are actually already performed by bsrl or xorl instructions.
And constant - __builtin_clz* can be simplified into
bsr + constant - bitmask.
For TARGET_LZCNT, a lot of this is already fine as is (e.g. the sign or
zero extensions), and other optimizations are IMHO not possible
(if we have lzcnt, we've lost information on whether it is UB at
zero or not and so can't transform it into bsr even when that is
1-2 insns shorter).
The changes on the 3 testcases between unpatched and patched gcc
are for -m64:
pr78103-1.s:
bsrq %rdi, %rax
- xorq $63, %rax
- cltq
+ xorl $63, %eax
...
bsrq %rdi, %rax
- xorq $63, %rax
- cltq
+ xorl $63, %eax
...
bsrl %edi, %eax
xorl $31, %eax
- cltq
...
bsrl %edi, %eax
xorl $31, %eax
- cltq
pr78103-2.s:
bsrl %edi, %edi
- movl $32, %eax
- xorl $31, %edi
- subl %edi, %eax
+ leal 1(%rdi), %eax
...
- bsrl %edi, %edi
- movl $31, %eax
- xorl $31, %edi
- subl %edi, %eax
+ bsrl %edi, %eax
...
bsrq %rdi, %rdi
- movl $64, %eax
- xorq $63, %rdi
- subl %edi, %eax
+ leal 1(%rdi), %eax
...
- bsrq %rdi, %rdi
- movl $63, %eax
- xorq $63, %rdi
- subl %edi, %eax
+ bsrq %rdi, %rax
pr78103-3.s:
bsrl %edi, %edi
- movl $32, %eax
- xorl $31, %edi
- movslq %edi, %rdi
- subq %rdi, %rax
+ leaq 1(%rdi), %rax
...
- bsrl %edi, %edi
- movl $31, %eax
- xorl $31, %edi
- movslq %edi, %rdi
- subq %rdi, %rax
+ bsrl %edi, %eax
...
bsrq %rdi, %rdi
- movl $64, %eax
- xorq $63, %rdi
- movslq %edi, %rdi
- subq %rdi, %rax
+ leaq 1(%rdi), %rax
...
- bsrq %rdi, %rdi
- movl $63, %eax
- xorq $63, %rdi
- movslq %edi, %rdi
- subq %rdi, %rax
+ bsrq %rdi, %rax
Most of the changes are done with combine splitters, but for
*bsr_rex64_2 and *bsr_2 I had to use define_insn_and_split, because
as mentioned in the PR the combiner unfortunately doesn't create LOG_LINKS
in between the two insns created by combine splitter, so it can't be
combined further with following instructions.
2021-07-31 Jakub Jelinek <jakub@redhat.com>
PR target/78103
* config/i386/i386.md (bsr_rex64_1, bsr_1, bsr_zext_1): New
define_insn patterns.
(*bsr_rex64_2, *bsr_2): New define_insn_and_split patterns.
Add combine splitters for constant - clz.
(clz<mode>2): Use a temporary pseudo for bsr result.
* gcc.target/i386/pr78103-1.c: New test.
* gcc.target/i386/pr78103-2.c: New test.
* gcc.target/i386/pr78103-3.c: New test.
Commit r12-432, rewriting the dg-stuff, reverted the
adjustment for mmix-knuth-mmixware that I added in r11-2335.
(See those commits for context.)
Hopefully this variant will age better, just skipping it
with a trivial extra line less prone to pile-on. (Not much
is won by covering this generic case for MMIX too; might as
well skip it.)
Beware that the dg-skip-if text can't say
"temporary variables are not x and y but x::3 and y::4"
because that leads to (on one line):
ERROR: gcc.dg/tree-ssa/ssa-dse-26.c: can't set "{temporary
variables are not x and y but x::3 and y::4} {
mmix-knuth-mmixware }": parent namespace doesn't exist for
" dg-skip-if 4 "temporary variables are not x and y but
x::3 and y::4" { mmix-knuth-mmixware } "
gcc/testsuite:
* gcc.dg/tree-ssa/ssa-dse-26.c: Skip on mmix-knuth-mmixware.
Add the tests for _mm_floor_pd, _mm_floor_ps, _mm_floor_sd, _mm_floor_ss.
These are modelled after (and depend upon parts of) the tests for
_mm_ceil intrinsics, recently posted.
Copy a test for _mm_floor_sd from gcc/testsuite/gcc.target/i386.
2021-07-30 Paul A. Clarke <pc@us.ibm.com>
gcc/testsuite
* gcc.target/powerpc/sse4_1-floorpd.c: New.
* gcc.target/powerpc/sse4_1-floorps.c: New.
* gcc.target/powerpc/sse4_1-floorsd.c: New.
* gcc.target/powerpc/sse4_1-floorss.c: New.
* gcc.target/powerpc/sse4_1-roundpd-2.c: Copy from
gcc/testsuite/gcc.target/i386 and adjust dg directives to suit.
Add the tests for _mm_ceil_pd, _mm_ceil_ps, _mm_ceil_sd, _mm_ceil_ss.
Copy a test for _mm_ceil_pd and _mm_ceil_ps from
gcc/testsuite/gcc.target/i386.
Define __VSX_SSE2__ to pick up some union definitions in
m128-check.h.
2021-07-30 Paul A. Clarke <pc@us.ibm.com>
gcc/testsuite
* gcc.target/powerpc/sse4_1-ceilpd.c: New.
* gcc.target/powerpc/sse4_1-ceilps.c: New.
* gcc.target/powerpc/sse4_1-ceilsd.c: New.
* gcc.target/powerpc/sse4_1-ceilss.c: New.
* gcc.target/powerpc/sse4_1-round-data.h: New.
* gcc.target/powerpc/sse4_1-round.h: New.
* gcc.target/powerpc/sse4_1-round2.h: New.
* gcc.target/powerpc/sse4_1-roundpd-3.c: Copy from gcc.target/i386
and adjust dg directives to suit.
* gcc.target/powerpc/sse4_1-check.h (__VSX_SSE2__): Define.
Copy the tests for _mm_blend_pd, _mm_blendv_pd, _mm_blend_ps,
_mm_blendv_ps from gcc/testsuite/gcc.target/i386.
2021-07-30 Paul A. Clarke <pc@us.ibm.com>
gcc/testsuite
* gcc.target/powerpc/sse4_1-blendpd.c: Copy from gcc.target/i386
and adjust dg directives to suit.
* gcc.target/powerpc/sse4_1-blendps-2.c: Likewise.
* gcc.target/powerpc/sse4_1-blendps.c: Likewise.
* gcc.target/powerpc/sse4_1-blendvpd.c: Likewise.
_mm_blend_epi16 and _mm_blendv_epi8 were added earlier.
Add these four to complete the set.
2021-07-30 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_blend_pd, _mm_blendv_pd,
_mm_blend_ps, _mm_blendv_ps): New.
The following patch to the x86_64 backend improves the code generated
for a decrement followed by a conditional move. The primary change is
to recognize that after subtracting one, checking the result is -1 (or
equivalently that the original value was zero) can be implemented using
the borrow/carry flag instead of requiring an explicit test instruction.
This is achieved by a new define_insn_and_split that allows combine to
split the desired sequence/composite into a *subsi_3 and *movsicc_noc.
The other change with this patch is/are a pair of peephole2 optimizations
to eliminate register-to-register moves generated during register
allocation. During reload, the compiler doesn't know that inverting
the condition of a conditional cmove can sometimes reduce register
pressure, but this is easy to tidy up during the peephole2 pass (where
swapping the order of the insn's operands performs the required
logic inversion).
Both improvements are demonstrated by the case below:
int foo(int x) {
if (x == 0)
x = 16;
else x--;
return x;
}
Before:
foo: leal -1(%rdi), %eax
testl %edi, %edi
movl $16, %edx
cmove %edx, %eax
ret
After:
foo: subl $1, %edi
movl $16, %eax
cmovnc %edi, %eax
ret
And the value of the peephole2 clean-up can be seen on its own in:
int bar(int x) {
x--;
if (x == 0)
x = 16;
return x;
}
Before:
bar: movl %edi, %eax
movl $16, %edx
subl $1, %eax
cmove %edx, %eax
ret
After:
bar: subl $1, %edi
movl $16, %eax
cmovne %edi, %eax
ret
These idioms were inspired by the source code of NIST SciMark4's
Random_nextDouble function, where the tweaks above result in
a ~1% improvement in the MonteCarlo benchmark kernel.
2021-07-30 Roger Sayle <roger@nextmovesoftware.com>
Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog
* config/i386/i386.md (*dec_cmov<mode>): New define_insn_and_split
to generate a conditional move using the carry flag after sub $1.
(peephole2): Eliminate a register-to-register move by inverting
the condition of a conditional move.
gcc/testsuite/ChangeLog
* gcc.target/i386/dec-cmov-1.c: New test.
* gcc.target/i386/dec-cmov-2.c: New test.
I guess the best way to describe these operands, at least for MMIX, is
"ballast". Some targets seem to drag along one or two of the incoming
pattern operands through the rtl passes and not dropping them until
assembly output. Let's stop doing that for MMIX. There really are
*two* unused parameters: one is a number corresponding to the
stack-size of arguments as a const_int and the other is whatever the
target yields for targetm.calls.function_arg (args_so_far,
function_arg_info::end_marker ()). There's a mandatory second
argument to the "call" RTX, but the target doesn't have to keep it a
variable number; it can be replaced by (const_int 0) early, like this.
Astute readers may object that as the MMIX call-type insns (PUSHJ,
PUSHGO) have a parameter in addition to the address of the called
function, so should the emitted RTL. But, that parameter depends only
on the local function, not the called function (IOW, it's the same for
all calls in a function), and its value isn't known until frame layout
time. Having it a parameter in the emitted RTL for the call would
just be confusing. (Maybe this will be amended later, if/when
improving "shrink-wrapping".)
gcc:
* config/mmix/mmix.md ("call", "call_value", "*call_real")
("*call_value_real"): Don't generate rtx mentioning the generic
operands 1 and 2 to "call", and similarly for "call_value".
* config/mmix/mmix.c (mmix_print_operand_punct_valid_p)
(mmix_print_operand): Use '!' instead of 'p'.
An old itch being scratched: the documentation lies; it's not "the
number of registers used as operands", unless the target makes a
special arrangement to that effect, and there's nothing in the guts of
gcc setting up or assuming those semantics.
Instead, see calls.c:expand_call, variable next_arg_reg. Or just
consider the variable name. The text is somewhat transcribed from the
head comment of emit_call_1 for parameter next_arg_reg. Most
important is to document the relation to function_arg_info::end_marker()
and the TARGET_FUNCTION_ARG hook.
The "normally" in the head comment, in "normally it is the first
arg-register beyond those used for args in this call, or 0 if all the
arg-registers are used in this call" means "by default", unless the
target tests end_marker_p and does something special, but the port is
free to return whatever it likes when it sees the end-marker.
And, I do mean "whatever it likes" because if the port doesn't
actually mention that operand in the RTX emitted for its "call" or
"call_value" patterns ("usually" define_expands), it can be any
mumbo-jumbo, such as a VOIDmode register, which seems like it happens
for some targets, or NULL, that happens for others. Returning a
VOIDmode register until recently included MMIX, where it made it into
the emitted RTL, confusing later passes, recently exposed as an ICE.
Tested by inspecting the info and generated pdf for sanity.
gcc:
* doc/md.texi (call): Correct information about operand 2.
* config/mmix/mmix.md ("call", "call_value"): Remove fixed FIXMEs.
Handle const % const, as wi_fold_in_parts may now provide this. Before this
[10, 10] % [4, 4] would produce [0, 3] instead of [2, 2].
gcc/
* range-op.cc (operator_trunc_mod::wi_fold): Fold constants.
gcc/testsuite/
* gcc.dg/tree-ssa/pr61839_2.c: Adjust. Add new const fold test.
Instead of VARYING, we can get better results by treating divide by zero
as producing an undefined result.
gcc/
* range-op.cc (operator_div::wi_fold): Return UNDEFINED for [0, 0] divisor.
gcc/testsuite/
* gcc.dg/tree-ssa/pr61839_2.c: Adjust.
1. Replace scalar_int_mode with fixed_size_mode in the by-pieces
infrastructure to allow non-integer mode.
2. Rename widest_int_mode_for_size to widest_fixed_size_mode_for_size
to return QI vector mode for memset.
3. Add op_by_pieces_d::smallest_fixed_size_mode_for_size to return the
smallest integer or QI vector mode.
4. Remove clear_by_pieces_1 and use builtin_memset_read_str in
clear_by_pieces to support vector mode broadcast.
5. Add lowpart_subreg_regno, a wrapper around simplify_subreg_regno that
uses subreg_lowpart_offset (mode, prev_mode) as the offset.
6. Add TARGET_GEN_MEMSET_SCRATCH_RTX to allow the backend to use a hard
scratch register to avoid stack realignment when expanding memset.
gcc/
PR middle-end/90773
* builtins.c (builtin_memcpy_read_str): Change the mode argument
from scalar_int_mode to fixed_size_mode.
(builtin_strncpy_read_str): Likewise.
(gen_memset_value_from_prev): New function.
(builtin_memset_read_str): Change the mode argument from
scalar_int_mode to fixed_size_mode. Use gen_memset_value_from_prev
and support CONST_VECTOR.
(builtin_memset_gen_str): Likewise.
(try_store_by_multiple_pieces): Use by_pieces_constfn to declare
constfun.
* builtins.h (builtin_strncpy_read_str): Replace scalar_int_mode
with fixed_size_mode.
(builtin_memset_read_str): Likewise.
* expr.c (widest_int_mode_for_size): Renamed to ...
(widest_fixed_size_mode_for_size): Add a bool argument to
indicate if QI vector mode can be used.
(by_pieces_ninsns): Call widest_fixed_size_mode_for_size
instead of widest_int_mode_for_size.
(pieces_addr::adjust): Change the mode argument from
scalar_int_mode to fixed_size_mode.
(op_by_pieces_d): Make m_len read-only. Add a bool member,
m_qi_vector_mode, to indicate that QI vector mode can be used.
(op_by_pieces_d::op_by_pieces_d): Add a bool argument to
initialize m_qi_vector_mode. Call widest_fixed_size_mode_for_size
instead of widest_int_mode_for_size.
(op_by_pieces_d::get_usable_mode): Change the mode argument from
scalar_int_mode to fixed_size_mode. Call
widest_fixed_size_mode_for_size instead of
widest_int_mode_for_size.
(op_by_pieces_d::smallest_fixed_size_mode_for_size): New member
function to return the smallest integer or QI vector mode.
(op_by_pieces_d::run): Call widest_fixed_size_mode_for_size
instead of widest_int_mode_for_size. Call
smallest_fixed_size_mode_for_size instead of
smallest_int_mode_for_size.
(store_by_pieces_d::store_by_pieces_d): Add a bool argument to
indicate that QI vector mode can be used and pass it to
op_by_pieces_d::op_by_pieces_d.
(can_store_by_pieces): Call widest_fixed_size_mode_for_size
instead of widest_int_mode_for_size. Pass memsetp to
widest_fixed_size_mode_for_size to support QI vector mode.
Allow all CONST_VECTORs for memset if vec_duplicate is supported.
(store_by_pieces): Pass memsetp to
store_by_pieces_d::store_by_pieces_d.
(clear_by_pieces_1): Removed.
(clear_by_pieces): Replace clear_by_pieces_1 with
builtin_memset_read_str and pass true to store_by_pieces_d to
support vector mode broadcast.
(string_cst_read_str): Change the mode argument from
scalar_int_mode to fixed_size_mode.
* expr.h (by_pieces_constfn): Change scalar_int_mode to
fixed_size_mode.
(by_pieces_prev): Likewise.
* rtl.h (lowpart_subreg_regno): New.
* rtlanal.c (lowpart_subreg_regno): New. A wrapper around
simplify_subreg_regno.
* target.def (gen_memset_scratch_rtx): New hook.
* doc/tm.texi.in: Add TARGET_GEN_MEMSET_SCRATCH_RTX.
* doc/tm.texi: Regenerated.
gcc/testsuite/
* gcc.target/i386/pr100865-3.c: Expect vmovdqu8 instead of
vmovdqu.
* gcc.target/i386/pr100865-4b.c: Likewise.
So I was looking at some older PRs (PR 16016 in this case),
I noticed that some of the testcases were removed when
the tree-ssa branch was merged. This adds them back in.
OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gcc/testsuite/ChangeLog:
PR testsuite/101517
* g++.dg/warn/Wunused-18.C: New test.
* gcc.c-torture/compile/20030405-2.c: New test.
* gcc.c-torture/compile/20040304-2.c: New test.
* gcc.dg/20030612-2.c: New test.
This adds a configure check for the GNU extension secure_getenv and then
uses it for looking up TMPDIR and similar variables.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
PR libstdc++/65018
* configure.ac: Check for secure_getenv.
* config.h.in: Regenerate.
* configure: Regenerate.
* src/filesystem/ops-common.h (get_temp_directory_from_env): New
helper function to obtain path from the environment.
* src/c++17/fs_ops.cc (fs::temp_directory_path): Use new helper.
* src/filesystem/ops.cc (fs::temp_directory_path): Likewise.
* testsuite/27_io/filesystem/operations/temp_directory_path.cc:
Print messages if test cannot be run.
* testsuite/experimental/filesystem/operations/temp_directory_path.cc:
Likewise. Fix incorrect condition. Use "TMP" to work with
Windows as well as POSIX.
Commit message shamelessly copied from 1777beb6b1 by jakub:
This function, because it is sometimes called even outside of function
bodies, uses create_tmp_var_raw rather than create_tmp_var. But in order
for that to work, when first referenced, the VAR_DECLs need to appear in a
TARGET_EXPR so that during gimplification the var gets the right
DECL_CONTEXT and is added to local decls.
gcc/
PR target/94780
* config/mips/mips.c (mips_atomic_assign_expand_fenv): Use
TARGET_EXPR instead of MODIFY_EXPR.
Middle-end started to emit vec_cmp and vec_cmpu since GCC 11, causing
ICE on MIPS with MSA enabled. Add the pattern to prevent it.
gcc/
PR target/101132
* config/mips/mips-protos.h (mips_expand_vec_cmp_expr): Declare.
* config/mips/mips.c (mips_expand_vec_cmp_expr): New function.
* config/mips/mips-msa.md (vec_cmp<MSA:mode><mode_i>): New
expander.
(vec_cmpu<IMSA:mode><mode_i>): New expander.
gcc/testsuite/
PR target/101132
* gcc.target/mips/pr101132.c: New test.
The following patch attempts to implement the compiler helpers for
libstdc++ std::is_pointer_interconvertible_base_of trait and
std::is_pointer_interconvertible_with_class template function.
For the former __is_pointer_interconvertible_base_of trait that checks first
whether base and derived aren't non-union class types that are the same
ignoring toplevel cv-qualifiers, otherwise if derived is unambiguously
derived from base without cv-qualifiers, derived being a complete type,
and if so, my limited understanding of any derived object being
pointer-interconvertible with base subobject IMHO implies (because one can't
inherit from unions or unions can't inherit) that we check if derived is
standard layout type and we walk bases of derived
recursively, stopping on a class that has any non-static data members and
check if any of the bases is base. On class with non-static data members
no bases are compared already.
Upon discussions, this is something that maybe should have been changed
in the standard with CWG 2254 and the patch no longer performs this and
assumes all base subobjects of standard-layout class types are
pointer-interconvertible with the whole class objects.
The latter is implemented using a FE
__builtin_is_pointer_interconvertible_with_class, but because on the library
side it will be a template function, the builtin takes ... arguments and
only during folding verifies it has a single argument with pointer to member
type. The initial errors IMHO can only happen if one uses the builtin
incorrectly by hand, the template function should ensure that it has
exactly a single argument that has pointer to member type.
Otherwise, again with my limited understanding of what
the template function should do and pointer-interconvertibility,
it folds to false for pointer-to-member-function, errors if
basetype of the OFFSET_TYPE is incomplete, folds to false
for non-std-layout non-union basetype, then finds the first non-static
data member in the basetype or its bases (by ignoring
DECL_FIELD_IS_BASE FIELD_DECLs that are empty, recursing into
DECL_FIELD_IS_BASE FIELD_DECLs type that are non-empty (I think
std layout should ensure there is at most one), for unions
checks if membertype is same type as any of the union FIELD_DECLs,
for non-unions the first other FIELD_DECL only, and for anonymous
aggregates similarly (union vs. non-union) but recurses into the
anon aggr types with std layout check for anon structures. If
membertype doesn't match the type of first non-static data member
(or for unions any of the members), then the builtin folds to false,
otherwise the built folds to a check whether the argument is equal
to OFFSET_TYPE of 0 or not, either at compile time if it is constant
(e.g. for constexpr folding) or at runtime otherwise.
As I wrote in the PR, I've tried my testcases with MSVC on godbolt
that claims to implement it, and https://godbolt.org/z/3PnjM33vM
for the first testcase shows it disagrees with my expectations on
static_assert (std::is_pointer_interconvertible_base_of_v<D, F>);
static_assert (std::is_pointer_interconvertible_base_of_v<E, F>);
static_assert (!std::is_pointer_interconvertible_base_of_v<D, G>);
static_assert (!std::is_pointer_interconvertible_base_of_v<D, I>);
static_assert (std::is_pointer_interconvertible_base_of_v<H, volatile I>);
Is that a bug in my patch or is MSVC buggy on these (or mix thereof)?
https://godbolt.org/z/aYeYnne9d
shows the second testcase, here it differs on:
static_assert (std::is_pointer_interconvertible_with_class<F, int> (&F::b));
static_assert (std::is_pointer_interconvertible_with_class<I, int> (&I::g));
static_assert (std::is_pointer_interconvertible_with_class<L, int> (&L::b));
static_assert (std::is_pointer_interconvertible_with_class (&V::a));
static_assert (std::is_pointer_interconvertible_with_class (&V::b));
Again, my bug, MSVC bug, mix thereof?
According to Jason the <D, G>, <D, I> case are the subject of the
CWG 2254 above discussed change and the rest are likely MSVC bugs.
Oh, and there is another thing, the standard has an example:
struct A { int a; }; // a standard-layout class
struct B { int b; }; // a standard-layout class
struct C: public A, public B { }; // not a standard-layout class
static_assert( is_pointer_interconvertible_with_class( &C::b ) );
// Succeeds because, despite its appearance, &C::b has type
// “pointer to member of B of type int”.
static_assert( is_pointer_interconvertible_with_class<C>( &C::b ) );
// Forces the use of class C, and fails.
It seems to work as written with MSVC (second assertion fails),
but fails with GCC with the patch:
/tmp/1.C:22:57: error: no matching function for call to ‘is_pointer_interconvertible_with_class<C>(int B::*)’
22 | static_assert( is_pointer_interconvertible_with_class<C>( &C::b ) );
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
/tmp/1.C:8:1: note: candidate: ‘template<class S, class M> constexpr bool std::is_pointer_interconvertible_with_class(M S::*)’
8 | is_pointer_interconvertible_with_class (M S::*m) noexcept
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/tmp/1.C:8:1: note: template argument deduction/substitution failed:
/tmp/1.C:22:57: note: mismatched types ‘C’ and ‘B’
22 | static_assert( is_pointer_interconvertible_with_class<C>( &C::b ) );
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
the second int argument isn't deduced.
This boils down to:
template <class S, class M>
bool foo (M S::*m) noexcept;
struct A { int a; };
struct B { int b; };
struct C : public A, public B {};
bool a = foo (&C::b);
bool b = foo<C, int> (&C::b);
bool c = foo<C> (&C::b);
which with /std:c++20 or -std=c++20 is accepted by latest MSVC and ICC but
rejected by GCC and clang (in both cases on the last line).
Is this a GCC/clang bug in argument deduction (in that case I think we want
a separate PR), or a bug in ICC/MSVC and the standard itself that should
specify in the examples both template arguments instead of just the first?
And this has been raised with the CWG.
2021-07-30 Jakub Jelinek <jakub@redhat.com>
PR c++/101539
gcc/c-family/
* c-common.h (enum rid): Add RID_IS_POINTER_INTERCONVERTIBLE_BASE_OF.
* c-common.c (c_common_reswords): Add
__is_pointer_interconvertible_base_of.
gcc/cp/
* cp-tree.h (enum cp_trait_kind): Add
CPTK_IS_POINTER_INTERCONVERTIBLE_BASE_OF.
(enum cp_built_in_function): Add
CP_BUILT_IN_IS_POINTER_INTERCONVERTIBLE_WITH_CLASS.
(fold_builtin_is_pointer_inverconvertible_with_class): Declare.
* parser.c (cp_parser_primary_expression): Handle
RID_IS_POINTER_INTERCONVERTIBLE_BASE_OF.
(cp_parser_trait_expr): Likewise.
* cp-objcp-common.c (names_builtin_p): Likewise.
* constraint.cc (diagnose_trait_expr): Handle
CPTK_IS_POINTER_INTERCONVERTIBLE_BASE_OF.
* decl.c (cxx_init_decl_processing): Register
__builtin_is_pointer_interconvertible_with_class builtin.
* constexpr.c (cxx_eval_builtin_function_call): Handle
CP_BUILT_IN_IS_POINTER_INTERCONVERTIBLE_WITH_CLASS builtin.
* semantics.c (pointer_interconvertible_base_of_p,
first_nonstatic_data_member_p,
fold_builtin_is_pointer_inverconvertible_with_class): New functions.
(trait_expr_value): Handle CPTK_IS_POINTER_INTERCONVERTIBLE_BASE_OF.
(finish_trait_expr): Likewise. Formatting fix.
* cp-gimplify.c (cp_gimplify_expr): Fold
CP_BUILT_IN_IS_POINTER_INTERCONVERTIBLE_WITH_CLASS. Call
fndecl_built_in_p just once.
(cp_fold): Likewise.
* tree.c (builtin_valid_in_constant_expr_p): Handle
CP_BUILT_IN_IS_POINTER_INTERCONVERTIBLE_WITH_CLASS. Call
fndecl_built_in_p just once.
* cxx-pretty-print.c (pp_cxx_trait_expression): Handle
CPTK_IS_POINTER_INTERCONVERTIBLE_BASE_OF.
gcc/testsuite/
* g++.dg/cpp2a/is-pointer-interconvertible-base-of1.C: New test.
* g++.dg/cpp2a/is-pointer-interconvertible-with-class1.C: New test.
* g++.dg/cpp2a/is-pointer-interconvertible-with-class2.C: New test.
* g++.dg/cpp2a/is-pointer-interconvertible-with-class3.C: New test.
* g++.dg/cpp2a/is-pointer-interconvertible-with-class4.C: New test.
* g++.dg/cpp2a/is-pointer-interconvertible-with-class5.C: New test.
* g++.dg/cpp2a/is-pointer-interconvertible-with-class6.C: New test.
In discussion of jakub's patch for C++20 pointer-interconvertibility, it
came up that we allow anonymous structs to have bases, but don't do anything
usable with them. Let's reject it.
The comment change is something I noticed while looking for the right place
to diagnose this: finish_struct_anon does not actually check for anything
invalid, so it shouldn't claim to.
gcc/cp/ChangeLog:
* class.c (finish_struct_anon): Improve comment.
* decl.c (fixup_anonymous_aggr): Reject anonymous struct
with bases.
gcc/testsuite/ChangeLog:
* g++.dg/ext/anon-struct8.C: New test.
During the OpenMP directives using C++ attribute syntax work, I've noticed
that cp_parser_statement when parsing various block declarations that do
not allow attribute-specifier-seq at the start rolls back the attributes
only if std_attrs is non-NULL (i.e. some attributes have been parsed),
but doesn't roll back if some tokens were parsed as attribute-specifier-seq,
but didn't yield any attributes (e.g. [[]][[]][[]][[]]), which means
we accept those empty attributes even in places where they don't appear
in the grammar.
The following patch fixes that by instead checking if there are any
tokens to roll back. This makes the parsing handle the first
function the same as the second one (where some attribute appears).
The testcase contains two xfails, using namespace ... apparently
allows attributes at the start and the attributes shall appeartain to
using in that case. To be fixed incrementally.
2021-07-30 Jakub Jelinek <jakub@redhat.com>
* parser.c (cp_parser_statement): Rollback attributes not just
when std_attrs is non-NULL, but whenever
cp_parser_std_attribute_spec_seq parsed any tokens.
* g++.dg/cpp0x/gen-attrs-76.C: New test.
gcc/
PR target/101685
* config/i386/i386-options.c (ix86_option_override_internal):
Don't enable LZCNT/POPCNT if they have been disabled explicitly.
gcc/testsuite/
PR target/101685
* gcc.target/i386/pr101685.c: New test.
The front-end ensures that both sides have been casted to the same type
before being given to the lowering pass.
gcc/d/ChangeLog:
* expr.cc (binary_op): Remove dead code.
Makes it explicit that the default value is set to NULL.
gcc/d/ChangeLog:
* typeinfo.cc (TypeInfoVisitor::visit (TypeInfoClassDeclaration *)):
Always layout initializer for the m_RTInfo field.
This expression is just discarded by add_stmt, so never reaches the
middle-end.
gcc/d/ChangeLog:
* expr.cc (ExprVisitor::visit (AssertExp *)): Don't generate
PREDICT_EXPR.
The code block is done as an optimization to elide a call to the runtime
library helpers _d_arrayctor or _d_arrayassign.
gcc/d/ChangeLog:
* expr.cc (ExprVisitor::visit (AssignExp *)): Clarify comment
for generating static array assignment with literal.
Anonymous enums neither generate an initializer nor typeinfo symbol, so
it's safe to assert that all enum declarations passed to this function
always have an identifier.
gcc/d/ChangeLog:
* decl.cc (enum_initializer_decl): Only handle named enums.
It is not expected to have a member function that can be non-public, but
this guards against any internal errors that might occur should that
ever change in the front-end.
gcc/d/ChangeLog:
* decl.cc (make_thunk): Set COMDAT and visibility of thunks only if
they are public.
The self-hosted implementation of the D front-end changes the type of
`sinit' to a void pointer, which requires an explicit cast to `tree'.
gcc/d/ChangeLog:
* decl.cc (DeclVisitor::visit (StructDeclaration *)): Don't use sinit
for declaration directly.
(DeclVisitor::visit (ClassDeclaration *)): Likewise.
(aggregate_initializer_decl): Likewise. Set sinit after creating.
The self-hosted implementation of the D front-end does not export
Identifier::generateId, so handle name generation inline instead.
gcc/d/ChangeLog:
* d-builtins.cc (build_frontend_type): Use Identifier::idPool to
generate anonymous field name.
This helper introduced by the front-end is a better gate, and allows the
front-end to change rules for what gets a monitor in the future.
gcc/d/ChangeLog:
* types.cc (layout_aggregate_type): Call hasMonitor.
* typeinfo.cc (TypeInfoVisitor::layout_base): Likewise.
(layout_cpp_typeinfo): Likewise. Don't emit vtable unless
have_typeinfo_p.
Covers cases where functions that handle the extracted strings ignore
the explicit length. This isn't something that's known to happen in the
current front-end, but the self-hosted front-end has been observed to do
this in its conversions between D and C-style strings.
gcc/d/ChangeLog:
* d-lang.cc (deps_add_target): Insert null terminator in buffer.
(deps_write): Likewise.
(d_parse_file): Likewise.
This ensures there are no dangling references to AST members that have
been freed, either explcitly or by the garbage collector.
gcc/d/ChangeLog:
* d-builtins.cc (build_frontend_type): Restore builtin_converted_decls
length on conversion failure.
Both do the exact same operation, just on different AST nodes.
gcc/d/ChangeLog:
* d-codegen.cc (d_nested_class): Rename to ...
(get_outer_function): ... this. Handle all aggregate declarations.
(d_nested_struct): Remove.
(find_this_tree): Use get_outer_function.
(get_framedecl): Likewise.
It occurs to me that I should not have disabled early jump threading in
this test, as it may hide an actual defect. I have reverted my change
and XFAILed the test instead. I have also opened a PR101690 to keep track
of this problem.
gcc/testsuite/ChangeLog:
* gcc.dg/shrink-wrap-loop.c: Enable early jump threading. Mark as
XFAIL.
gcc/ChangeLog:
PR target/66791
* config/arm/arm_neon.h (vld1_p64): Replace call to builtin by
explicitly dereferencing __a.
(vld1_s64): Likewise.
(vld1_u64): Likewise.
* config/arm/arm_neon_builtins.def (vld1): Remove entry for di
and change to VAR13.
This patch replaces the evrp_range_analyzer in the loop versioning code
with an on-demand ranger.
Tested on x86-64 Linux.
gcc/ChangeLog:
* gimple-loop-versioning.cc (lv_dom_walker::lv_dom_walker): Remove
use of m_range_analyzer.
(loop_versioning::lv_dom_walker::before_dom_children): Same.
(loop_versioning::lv_dom_walker::after_dom_children): Remove.
(loop_versioning::prune_loop_conditions): Replace vr_values use
with range_query interface.
(pass_loop_versioning::execute): Use ranger.
As the following testcase shows, we don't parse properly
C++11 attribute-declaration:
https://eel.is/c++draft/dcl.dcl#nt:attribute-declaration
cp_parser_toplevel_declaration just handles empty-declaration parsing
(with diagnostics for C++98) and otherwise calls cp_parser_declaration
which on it calls cp_parser_simple_declaration and rejects it with
"does not declare anything" permerror.
The following patch moves the handling of empty-declaration from
cp_parser_toplevel_declaration to cp_parser_declaration and
handles attribute-declaration in cp_parser_declaration
by parsing the attributes (standard ones only, we've never supported
__attribute__((...)); at namespace scope, so I'm not sure we need to
introduce that), which for C++98 emits the needed diagnostics, and then
warning if there are any attributes that we throw away on the floor.
I'll need this later for OpenMP directives at namespace scope, e.g.
[[omp::directive (requires, atomic_default_mem_order(seq_cst))]];
should be valid at namespace scope (and many other directives).
2021-07-30 Jakub Jelinek <jakub@redhat.com>
PR c++/101582
* parser.c (cp_parser_skip_std_attribute_spec_seq): Add a forward
declaration.
(cp_parser_declaration): Parse empty-declaration and
attribute-declaration.
(cp_parser_toplevel_declaration): Don't parse empty-declaration here.
* g++.dg/cpp0x/gen-attrs-45.C: Expect a warning about ignored
attributes instead of error.
* g++.dg/cpp0x/gen-attrs-75.C: New test.
* g++.dg/modules/pr101582-1.C: New test.
We are comparing enum values (in wide_int) to check ODR violation.
However, if we compare two wide_int values with different precision,
we'll trigger an assert, leading to ICE. With enum-base introduced
in C++11, it's easy to sink into this situation.
To fix the issue, we need to explicitly check this kind of mismatch,
and emit a proper warning message if there is such one.
gcc/
PR ipa/101396
* ipa-devirt.c (ipa_odr_read_section): Compare the precision of
enum values, and emit a warning if they mismatch.
gcc/testsuite/
PR ipa/101396
* g++.dg/lto/pr101396_0.C: New test.
* g++.dg/lto/pr101396_1.C: New test.
Commit r12-2534 was incomplete and (by inspection derived
from an MMIX build) failing for targets without an insn for
compare_and_swap for pointer-size objects, IOW for targets
for which "ATOMIC_POINTER_LOCK_FREE != 2" is true:
x/gcc/libstdc++-v3/src/c++17/memory_resource.cc: In member function
'std::pmr::memory_resource*
std::pmr::{anonymous}::atomic_mem_res::exchange(std::pmr::memory_resource*)':
x/gcc/libstdc++-v3/src/c++17/memory_resource.cc:140:21: error:
'exchange' is not a member of 'std'
140 | return std::exchange(val, r);
| ^~~~~~~~
make[5]: *** [Makefile:577: memory_resource.lo] Error 1
make[5]: Leaving directory
'/home/hp/tmp/newmmix-r12-2579-p3/gccobj/mmix/libstdc++-v3/src/c++17'
This fix was derived from edits elsewhere in that patch.
Tested mmix-knuth-mmixware, restoring build (together with
target-reviving patches as MMIX is currently and at that commit
broken for target-specific reasons).
libstdc++-v3/:
* src/c++17/memory_resource.cc: Use __exchange instead
of std::exchange.
This bug made me dive into some of the murkier waters of gcc, namely
the source of operand 2 to the "call" pattern. It can be pretty
poisonous, but is unused (either directly or later) by most targets.
The target function_arg (and function_incoming_arg), can unless
specially handled, cause a VOIDmode reg RTX to be generated, for the
function arguments end-marker. This is then passed on by expand_call
to the target "call" pattern, as operand[2] (which is wrongly
documented or wrongly implemented, see comment in mmix.c) but unused
by most targets that do not handle it specially, as in operand 2 not
making it into the insn generated for the "call" (et al) patterns. Of
course, the MMIX port stands out here: the RTX makes it into the
generated RTX but is then actually unused and is just a placeholder;
see mmix_print_operand 'p'.
Anyway, df-scan inspects the emitted call rtx and horks on the
void-mode RTX (actually: that it represents a zero-sized register
range) from r12-1702.
While I could replace or remove the emitted unused call insn operand,
that would still leave unusable rtx to future users of function_arg
actually looking for next_arg_reg. Better replace VOIDmode with
DImode here; that's the "natural" mode of MMIX registers.
(As a future improvement, I'll also remove the placeholder argument
and replace the intended user; the print_operand output modifier 'p'
modifier (as in "PUSHJ $%p2,%0") with some punctuation, perhaps '!'
(as in "PUSHJ $%!,%0").
I inspected all ports, but other targets emit a special
function_arg_info::end_marker cookie or just don't emit "call"
operand[2] (etc) in the expanded "call" pattern.
gcc:
* config/mmix/mmix.c (mmix_function_arg_1): Avoid
generating a VOIDmode register for e.g the
function_arg_info::end_marker.
gcc/
* config/h8300/h8300-modes.def: Add CCZ, CCV and CCC, drop CCZNV.
* config/h8300/h8300.md (H8cc mode iterator): Add CCZ.
(cc mode_attr): Similarly.
(ccz subst_attr): Similarly.
* config/h8300/jumpcall.md: Add new patterns for branch-on-bit.
* config/h8300/testcompare.md: Remove various cc0 based patterns
that had been commented out. Add pattern to set CCZ from a bit
test.
Related to:
PR middle-end/101674 - gcc.dg/uninit-pred-9_b.c fails after jump threading rewrite
gcc/testsuite:
PR middle-end/101674
* gcc.dg/uninit-pred-9_b.c: Xfail just the failing assertion and
correct target.
