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re PR target/27861 (ICE in expand_expr_real_1, at expr.c:6916)
PR target/27861 * expmed.c (expand_shift): On SHIFT_COUNT_TRUNCATED targets, we may have stripped a SUBREG from the shift count, so we may need to convert_to_mode back to the type's mode before calling make_tree. Use new_amount instead of amount to avoid expanding a tree twice. * gcc.dg/pr27861-1.c: New test case. From-SVN: r114773
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@ -1,3 +1,11 @@
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2006-06-19 Roger Sayle <roger@eyesopen.com>
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PR target/27861
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* expmed.c (expand_shift): On SHIFT_COUNT_TRUNCATED targets, we may
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have stripped a SUBREG from the shift count, so we may need to
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convert_to_mode back to the type's mode before calling make_tree.
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Use new_amount instead of amount to avoid expanding a tree twice.
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2006-06-19 Richard Guenther <rguenther@suse.de>
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PR middle-end/28045
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10
gcc/expmed.c
10
gcc/expmed.c
@ -2260,13 +2260,17 @@ expand_shift (enum tree_code code, enum machine_mode mode, rtx shifted,
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code below. */
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rtx subtarget = target == shifted ? 0 : target;
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tree new_amount, other_amount;
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rtx temp1;
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tree type = TREE_TYPE (amount);
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tree new_amount = make_tree (type, op1);
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tree other_amount
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if (GET_MODE (op1) != TYPE_MODE (type)
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&& GET_MODE (op1) != VOIDmode)
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op1 = convert_to_mode (TYPE_MODE (type), op1, 1);
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new_amount = make_tree (type, op1);
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other_amount
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= fold_build2 (MINUS_EXPR, type,
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build_int_cst (type, GET_MODE_BITSIZE (mode)),
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amount);
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new_amount);
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shifted = force_reg (mode, shifted);
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@ -1,3 +1,8 @@
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2006-06-19 Roger Sayle <roger@eyesopen.com>
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PR target/27861
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* gcc.dg/pr27861-1.c: New test case.
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2006-06-19 Richard Guenther <rguenther@suse.de>
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PR middle-end/28045
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67
gcc/testsuite/gcc.dg/pr27861-1.c
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67
gcc/testsuite/gcc.dg/pr27861-1.c
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@ -0,0 +1,67 @@
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/* PR target/27861 */
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/* The following code used to cause an ICE during RTL expansion, as
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expand shift was stripping the SUBREG of a rotate shift count, and
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later producing a VAR_DECL tree whose DECL_RTL's mode didn't match
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the VAR_DECL's type's mode. */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef struct sim_state *SIM_DESC;
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typedef enum
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{
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SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG
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}
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SIM_RC;
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typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__)));
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typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__)));
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typedef unsigned32 unsigned_address;
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typedef unsigned_address address_word;
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static __inline__ unsigned64
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__attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift)
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{
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unsigned64 result;
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result = (((val) >> (shift)) | ((val) << ((64) - (shift))));
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return result;
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}
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typedef struct _sim_cpu sim_cpu;
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enum
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{
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TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX,
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};
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typedef struct _trace_data
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{
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char trace_flags[32];
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}
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TRACE_DATA;
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typedef enum
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{
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nr_watchpoint_types,
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}
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watchpoint_type;
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typedef struct _sim_watchpoints
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{
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TRACE_DATA trace_data;
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}
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sim_cpu_base;
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struct _sim_cpu
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{
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sim_cpu_base base;
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};
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struct sim_state
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{
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sim_cpu cpu[1];
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};
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typedef address_word instruction_address;
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do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x,
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unsigned64 y)
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{
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unsigned64 result;
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result = ROTR64 (x, y);
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{
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if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0
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&& (((&(((&(sd)->cpu[0])))->base.trace_data))->
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trace_flags)[TRACE_ALU_IDX] != 0))
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trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result));
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}
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}
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